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cfg_usb_otg_hs_phy_utmi.h File Reference

Common configuration for STM32 OTG HS peripheral with internal UTMI HS PHY. More...

Detailed Description

Common configuration for STM32 OTG HS peripheral with internal UTMI HS PHY.

All STM32 boards which use the internal UTMI HS PHY for the USB OTG HS peripheral use the same configuration. Therefore a common configuration file can be used for these boards.

Author
Koen Zandberg koen@.nosp@m.berg.nosp@m.zand..nosp@m.net
Gunar Schorcht gunar.nosp@m.@sch.nosp@m.orcht.nosp@m..net

Definition in file cfg_usb_otg_hs_phy_utmi.h.

#include "periph_cpu.h"
#include "usbdev_synopsys_dwc2.h"
+ Include dependency graph for cfg_usb_otg_hs_phy_utmi.h:

Go to the source code of this file.

#define DWC2_USB_OTG_HS_ENABLED
 Enable the high speed USB OTG peripheral.
 
#define USBPHYC_TUNE_VALUE   0x00000f13U
 Default value of USBPHYC tuning control register.
 
#define USBDEV_NUMOF   ARRAY_SIZE(dwc2_usb_otg_fshs_config)
 Number of available USB OTG peripherals.
 
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config []
 Common USB OTG HS configuration.
 

Macro Definition Documentation

◆ DWC2_USB_OTG_HS_ENABLED

#define DWC2_USB_OTG_HS_ENABLED

Enable the high speed USB OTG peripheral.

Definition at line 38 of file cfg_usb_otg_hs_phy_utmi.h.

◆ USBDEV_NUMOF

#define USBDEV_NUMOF   ARRAY_SIZE(dwc2_usb_otg_fshs_config)

Number of available USB OTG peripherals.

Definition at line 78 of file cfg_usb_otg_hs_phy_utmi.h.

◆ USBPHYC_TUNE_VALUE

#define USBPHYC_TUNE_VALUE   0x00000f13U

Default value of USBPHYC tuning control register.

The value of the USBPHYC tuning control register (USBPHYC_TUNE) is used by the USB HS PHY controller for the tuning interface of the internal USB HS PHY, please refer the Reference Manual for STM32F72xxx and STM32F73xxx for details.

The value as defined in the [STM32CubeF7 HAL Driver MCU Component for F7] (https://bit.ly/3es9eFA) is used as default value. If necessary, it can be overridden by the board configuration in periph_conf.h by defining the value before this file is included.

Definition at line 54 of file cfg_usb_otg_hs_phy_utmi.h.

Variable Documentation

◆ dwc2_usb_otg_fshs_config

const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
static
Initial value:
= {
{
.periph = USB_OTG_HS_PERIPH_BASE,
.type = DWC2_USB_OTG_HS,
.rcc_mask = RCC_AHB1ENR_OTGHSEN,
.irqn = OTG_HS_IRQn,
.ahb = AHB1,
.dm = GPIO_PIN(PORT_B, 14),
.dp = GPIO_PIN(PORT_B, 15),
.af = GPIO_AF10,
.phy_tune = USBPHYC_TUNE_VALUE,
}
}
@ PORT_B
port B
Definition periph_cpu.h:48
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define USBPHYC_TUNE_VALUE
Default value of USBPHYC tuning control register.
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:113
@ DWC2_USB_OTG_PHY_UTMI
UTMI for internal HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.

Common USB OTG HS configuration.

Definition at line 60 of file cfg_usb_otg_hs_phy_utmi.h.