cc2538_sys_ctrl.h
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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef CC2538_SYS_CTRL_H
21 #define CC2538_SYS_CTRL_H
22 
23 #include "cc2538.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
32 typedef struct {
33 
37  union {
39  struct {
52  } CLOCK_CTRLbits;
53  } cc2538_sys_ctrl_clk_ctrl;
54 
58  union {
60  struct {
61  cc2538_reg_t SYS_DIV : 3;
63  cc2538_reg_t IO_DIV : 3;
65  cc2538_reg_t OSC : 1;
66  cc2538_reg_t OSC_PD : 1;
72  cc2538_reg_t OSC32K : 1;
76  } CLOCK_STAbits;
77  } cc2538_sys_ctrl_clk_sta;
78 
91  union {
93  struct {
97  } RCGCUARTbits;
98  } cc2538_sys_ctrl_unnamed1;
99 
103  union {
105  struct {
106  cc2538_reg_t UART0 : 1;
107  cc2538_reg_t UART1 : 1;
108  cc2538_reg_t RESERVED : 30;
109  } SCGCUARTbits;
110  } cc2538_sys_ctrl_unnamed2;
111 
115  union {
117  struct {
118  cc2538_reg_t UART0 : 1;
119  cc2538_reg_t UART1 : 1;
120  cc2538_reg_t RESERVED : 30;
121  } DCGCUARTbits;
122  } cc2538_sys_ctrl_unnamed3;
123 
135  cc2538_reg_t RESERVED10[5];
137  cc2538_reg_t RESERVED11[2];
139  cc2538_reg_t RESERVED12[4];
142  cc2538_reg_t RESERVED13[3];
148 
149 #define SYS_CTRL ( (cc2538_sys_ctrl_t*)0x400d2000 )
154 #define sys_clock_freq() ((SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
155  RCOSC16M_FREQ : XOSC32M_FREQ) >> \
156  SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV )
157 
158 #ifdef __cplusplus
159 } /* end extern "C" */
160 #endif
161 
162 #endif /* CC2538_SYS_CTRL_H */
163 
cc2538_reg_t SRCRC
CRC on state retention.
cc2538_reg_t AMP_DET
Amplitude detector of XOSC during power up.
cc2538_reg_t RESERVED8
Reserved bits.
cc2538_reg_t XOSC_STB
XOSC stable status.
cc2538_reg_t SYS_DIV
System clock rate setting.
cc2538_reg_t RESERVED5
Reserved bits.
cc2538_reg_t RCGCGPT
Module clocks for GPT[3:0] when the CPU is in active (run) mode.
cc2538_reg_t RESERVED1
Reserved bits.
cc2538_reg_t OSC32K
32-kHz clock oscillator selection
cc2538_reg_t RESERVED7
Reserved bits.
cc2538_uart_t *const UART0
UART0 Instance.
cc2538_reg_t IWE
This register controls interrupt wake-up.
cc2538_reg_t DCGCSEC
Module clocks for the security module when the CPU is in PM0.
cc2538_reg_t SCGCSEC
Module clocks for the security module when the CPU is in sleep mode.
cc2538_reg_t UART1
Enable UART1 clock in active (run) mode.
cc2538_reg_t EMUOVR
This register defines the emulator override controls for power mode and peripheral clock gate...
cc2538_reg_t UART0
Enable UART0 clock in active (run) mode.
cc2538_reg_t RESERVED4
Reserved bits.
cc2538_reg_t SRGPT
Reset for GPT[3:0].
cc2538_reg_t SRI2C
Reset for I2C.
cc2538_reg_t CLOCK_STA
Clock status register.
cc2538_reg_t RCGCI2C
Module clocks for I2C when the CPU is in active (run) mode.
cc2538_reg_t PWRDBG
Power debug register.
cc2538_reg_t RESERVED2
Reserved bits.
cc2538_reg_t HSOSC_STB
HSOSC stable status.
cc2538_reg_t SYNC_32K
32-kHz clock source synced to undivided system clock (16 or 32 MHz)
cc2538_reg_t RCGCUART
Module clocks for UART[1:0] when the CPU is in active (run) mode.
cc2538_reg_t I_MAP
This register selects which interrupt map to be used.
CC2538 MCU interrupt and register definitions.
cc2538_reg_t SOURCE_CHANGE
System clock source change.
cc2538_reg_t PMCTL
Power mode.
cc2538_reg_t SRUART
Reset for UART[1:0].
cc2538_reg_t RCGCSSI
Module clocks for SSI[1:0] when the CPU is in active (run) mode.
cc2538_reg_t RESERVED6
Reserved bits.
cc2538_reg_t OSC
System clock oscillator selection.
cc2538_reg_t DCGCI2C
Module clocks for I2C when the CPU is in PM0.
cc2538_reg_t CLD
This register controls the clock loss detection feature.
cc2538_reg_t SCGCUART
Module clocks for UART[1:0] when the CPU is in sleep mode.
cc2538_reg_t IO_DIV
I/O clock rate setting.
System Control component registers.
cc2538_reg_t CLOCK_CTRL
Clock control register.
cc2538_reg_t SCGCRFC
This register defines the module clocks for RF CORE when the CPU is in sleep mode.
cc2538_reg_t SCGCSSI
Module clocks for SSI[1:0] when the CPU is insSleep mode.
cc2538_reg_t RST
Last source of reset.
cc2538_reg_t OSC32K_CADIS
Disable calibration 32-kHz RC oscillator.
cc2538_reg_t SCGCGPT
Module clocks for GPT[3:0] when the CPU is in sleep mode.
cc2538_reg_t DCGCGPT
Module clocks for GPT[3:0] when the CPU is in PM0.
cc2538_reg_t DCGCRFC
This register defines the module clocks for RF CORE when the CPU is in PM0.
cc2538_reg_t SRSSI
Reset for SSI[1:0].
cc2538_reg_t RCGCRFC
This register defines the module clocks for RF CORE when the CPU is in active (run) mode...
cc2538_reg_t OSC32K_CALDIS
Disable calibration 32-kHz RC oscillator.
cc2538_reg_t DCGCUART
Module clocks for UART[1:0] when the CPU is in PM0.
cc2538_reg_t RESERVED
Reserved bits.
cc2538_reg_t DCGCSSI
Module clocks for SSI[1:0] when the CPU is in PM0.
cc2538_reg_t RESERVED3
Reserved bits.
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:124
cc2538_reg_t SCGCI2C
Module clocks for I2C when the CPU is in sleep mode.
cc2538_reg_t RESERVED9
Reserved bits.
cc2538_reg_t SRSEC
Reset for the security module.
cc2538_reg_t RCGCSEC
Module clocks for the security module when the CPU is in active (run) mode.
cc2538_uart_t *const UART1
UART1 Instance.
cc2538_reg_t OSC_PD
Oscillator power-down.