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cc2538.h
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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef _CC2538_
20 #define _CC2538_
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 /* ************************************************************************** */
27 /* CMSIS DEFINITIONS FOR CC2538 */
28 /* ************************************************************************** */
31 
33 typedef enum IRQn
34 {
35  /****** Cortex-M3 Processor Exceptions Numbers ****************************/
40  BusFault_IRQn = -11,
42  SVCall_IRQn = - 5,
44  PendSV_IRQn = - 2,
45  SysTick_IRQn = - 1,
47  /****** CC2538 specific Interrupt Numbers *********************************/
52  UART0_IRQn = 5,
53  UART1_IRQn = 6,
54  SSI0_IRQn = 7,
55  I2C_IRQn = 8,
56  ADC_IRQn = 14,
57  WDT_IRQn = 18,
64  ADC_CMP_IRQn = 25,
69  AES_ALT_IRQn = 30,
70  PKA_ALT_IRQn = 31,
73  SSI1_IRQn = 34,
76  UDMA_IRQn = 46,
78  USB_IRQn = 140,
79  RF_RXTX_IRQn = 141,
80  RF_ERR_IRQn = 142,
81  AES_IRQn = 143,
82  PKA_IRQn = 144,
83  SM_TIMER_IRQn = 145,
84  MACTIMER_IRQn = 146,
87 } IRQn_Type;
88 
92 void Reset_Handler(void);
93 void NMI_Handler(void);
94 void HardFault_Handler(void);
95 void MemManage_Handler(void);
96 void BusFault_Handler(void);
97 void UsageFault_Handler(void);
98 void SVC_Handler(void);
99 void DebugMon_Handler(void);
100 void PendSV_Handler(void);
101 void SysTick_Handler(void);
108 #define __CM3_REV 0x0200
109 #define __MPU_PRESENT 1
110 #define __NVIC_PRIO_BITS 3
111 #define __Vendor_SysTickConfig 0
117 #include <core_cm3.h>
118 
121 #define IEEE_ADDR_MSWORD ( *(const uint32_t*)0x00280028 )
122 #define IEEE_ADDR_LSWORD ( *(const uint32_t*)0x0028002c )
124 typedef volatile uint32_t cc2538_reg_t;
130 #define FLASH_BASE 0x00200000
131 #define SRAM_BASE 0x20000000
132 #define PERIPH_BASE 0x40000000
134 #define SRAM_BB_BASE 0x22000000
141 #define SSI0_CR0 ( *(cc2538_reg_t*)0x40008000 )
142 #define SSI0_CR1 ( *(cc2538_reg_t*)0x40008004 )
143 #define SSI0_DR ( *(cc2538_reg_t*)0x40008008 )
144 #define SSI0_SR ( *(cc2538_reg_t*)0x4000800c )
145 #define SSI0_CPSR ( *(cc2538_reg_t*)0x40008010 )
146 #define SSI0_IM ( *(cc2538_reg_t*)0x40008014 )
147 #define SSI0_RIS ( *(cc2538_reg_t*)0x40008018 )
148 #define SSI0_MIS ( *(cc2538_reg_t*)0x4000801c )
149 #define SSI0_ICR ( *(cc2538_reg_t*)0x40008020 )
150 #define SSI0_DMACTL ( *(cc2538_reg_t*)0x40008024 )
151 #define SSI0_CC ( *(cc2538_reg_t*)0x40008fc8 )
152 #define SSI1_CR0 ( *(cc2538_reg_t*)0x40009000 )
153 #define SSI1_CR1 ( *(cc2538_reg_t*)0x40009004 )
154 #define SSI1_DR ( *(cc2538_reg_t*)0x40009008 )
155 #define SSI1_SR ( *(cc2538_reg_t*)0x4000900c )
156 #define SSI1_CPSR ( *(cc2538_reg_t*)0x40009010 )
157 #define SSI1_IM ( *(cc2538_reg_t*)0x40009014 )
158 #define SSI1_RIS ( *(cc2538_reg_t*)0x40009018 )
159 #define SSI1_MIS ( *(cc2538_reg_t*)0x4000901c )
160 #define SSI1_ICR ( *(cc2538_reg_t*)0x40009020 )
161 #define SSI1_DMACTL ( *(cc2538_reg_t*)0x40009024 )
162 #define SSI1_CC ( *(cc2538_reg_t*)0x40009fc8 )
163 #define UART0_DR ( *(cc2538_reg_t*)0x4000c000 )
164 #define UART0_ECR ( *(cc2538_reg_t*)0x4000c004 )
165 #define UART0_RSR ( *(cc2538_reg_t*)0x4000c004 )
166 #define UART0_FR ( *(cc2538_reg_t*)0x4000c018 )
167 #define UART0_ILPR ( *(cc2538_reg_t*)0x4000c020 )
168 #define UART0_IBRD ( *(cc2538_reg_t*)0x4000c024 )
169 #define UART0_FBRD ( *(cc2538_reg_t*)0x4000c028 )
170 #define UART0_LCRH ( *(cc2538_reg_t*)0x4000c02c )
171 #define UART0_CTL ( *(cc2538_reg_t*)0x4000c030 )
172 #define UART0_IFLS ( *(cc2538_reg_t*)0x4000c034 )
173 #define UART0_IM ( *(cc2538_reg_t*)0x4000c038 )
174 #define UART0_RIS ( *(cc2538_reg_t*)0x4000c03c )
175 #define UART0_MIS ( *(cc2538_reg_t*)0x4000c040 )
176 #define UART0_ICR ( *(cc2538_reg_t*)0x4000c044 )
177 #define UART0_DMACTL ( *(cc2538_reg_t*)0x4000c048 )
178 #define UART0_LCTL ( *(cc2538_reg_t*)0x4000c090 )
179 #define UART0_LSS ( *(cc2538_reg_t*)0x4000c094 )
180 #define UART0_LTIM ( *(cc2538_reg_t*)0x4000c098 )
181 #define UART0_NINEBITADDR ( *(cc2538_reg_t*)0x4000c0a4 )
182 #define UART0_NINEBITAMASK ( *(cc2538_reg_t*)0x4000c0a8 )
183 #define UART0_PP ( *(cc2538_reg_t*)0x4000cfc0 )
184 #define UART0_CC ( *(cc2538_reg_t*)0x4000cfc8 )
185 #define UART1_DR ( *(cc2538_reg_t*)0x4000d000 )
186 #define UART1_ECR ( *(cc2538_reg_t*)0x4000d004 )
187 #define UART1_RSR ( *(cc2538_reg_t*)0x4000d004 )
188 #define UART1_FR ( *(cc2538_reg_t*)0x4000d018 )
189 #define UART1_ILPR ( *(cc2538_reg_t*)0x4000d020 )
190 #define UART1_IBRD ( *(cc2538_reg_t*)0x4000d024 )
191 #define UART1_FBRD ( *(cc2538_reg_t*)0x4000d028 )
192 #define UART1_LCRH ( *(cc2538_reg_t*)0x4000d02c )
193 #define UART1_CTL ( *(cc2538_reg_t*)0x4000d030 )
194 #define UART1_IFLS ( *(cc2538_reg_t*)0x4000d034 )
195 #define UART1_IM ( *(cc2538_reg_t*)0x4000d038 )
196 #define UART1_RIS ( *(cc2538_reg_t*)0x4000d03c )
197 #define UART1_MIS ( *(cc2538_reg_t*)0x4000d040 )
198 #define UART1_ICR ( *(cc2538_reg_t*)0x4000d044 )
199 #define UART1_DMACTL ( *(cc2538_reg_t*)0x4000d048 )
200 #define UART1_LCTL ( *(cc2538_reg_t*)0x4000d090 )
201 #define UART1_LSS ( *(cc2538_reg_t*)0x4000d094 )
202 #define UART1_LTIM ( *(cc2538_reg_t*)0x4000d098 )
203 #define UART1_NINEBITADDR ( *(cc2538_reg_t*)0x4000d0a4 )
204 #define UART1_NINEBITAMASK ( *(cc2538_reg_t*)0x4000d0a8 )
205 #define UART1_PP ( *(cc2538_reg_t*)0x4000dfc0 )
206 #define UART1_CC ( *(cc2538_reg_t*)0x4000dfc8 )
207 #define I2CM_SA ( *(cc2538_reg_t*)0x40020000 )
208 #define I2CM_CTRL ( *(cc2538_reg_t*)0x40020004 )
209 #define I2CM_STAT ( *(cc2538_reg_t*)0x40020004 )
210 #define I2CM_DR ( *(cc2538_reg_t*)0x40020008 )
211 #define I2CM_TPR ( *(cc2538_reg_t*)0x4002000c )
212 #define I2CM_IMR ( *(cc2538_reg_t*)0x40020010 )
213 #define I2CM_RIS ( *(cc2538_reg_t*)0x40020014 )
214 #define I2CM_MIS ( *(cc2538_reg_t*)0x40020018 )
215 #define I2CM_ICR ( *(cc2538_reg_t*)0x4002001c )
216 #define I2CM_CR ( *(cc2538_reg_t*)0x40020020 )
217 #define I2CS_OAR ( *(cc2538_reg_t*)0x40020800 )
218 #define I2CS_CTRL ( *(cc2538_reg_t*)0x40020804 )
219 #define I2CS_STAT ( *(cc2538_reg_t*)0x40020804 )
220 #define I2CS_DR ( *(cc2538_reg_t*)0x40020808 )
221 #define I2CS_IMR ( *(cc2538_reg_t*)0x4002080c )
222 #define I2CS_RIS ( *(cc2538_reg_t*)0x40020810 )
223 #define I2CS_MIS ( *(cc2538_reg_t*)0x40020814 )
224 #define I2CS_ICR ( *(cc2538_reg_t*)0x40020818 )
225 #define GPTIMER0_CFG ( *(cc2538_reg_t*)0x40030000 )
226 #define GPTIMER0_TAMR ( *(cc2538_reg_t*)0x40030004 )
227 #define GPTIMER0_TBMR ( *(cc2538_reg_t*)0x40030008 )
228 #define GPTIMER0_CTL ( *(cc2538_reg_t*)0x4003000c )
229 #define GPTIMER0_SYNC ( *(cc2538_reg_t*)0x40030010 )
230 #define GPTIMER0_IMR ( *(cc2538_reg_t*)0x40030018 )
231 #define GPTIMER0_RIS ( *(cc2538_reg_t*)0x4003001c )
232 #define GPTIMER0_MIS ( *(cc2538_reg_t*)0x40030020 )
233 #define GPTIMER0_ICR ( *(cc2538_reg_t*)0x40030024 )
234 #define GPTIMER0_TAILR ( *(cc2538_reg_t*)0x40030028 )
235 #define GPTIMER0_TBILR ( *(cc2538_reg_t*)0x4003002c )
236 #define GPTIMER0_TAMATCHR ( *(cc2538_reg_t*)0x40030030 )
237 #define GPTIMER0_TBMATCHR ( *(cc2538_reg_t*)0x40030034 )
238 #define GPTIMER0_TAPR ( *(cc2538_reg_t*)0x40030038 )
239 #define GPTIMER0_TBPR ( *(cc2538_reg_t*)0x4003003c )
240 #define GPTIMER0_TAPMR ( *(cc2538_reg_t*)0x40030040 )
241 #define GPTIMER0_TBPMR ( *(cc2538_reg_t*)0x40030044 )
242 #define GPTIMER0_TAR ( *(cc2538_reg_t*)0x40030048 )
243 #define GPTIMER0_TBR ( *(cc2538_reg_t*)0x4003004c )
244 #define GPTIMER0_TAV ( *(cc2538_reg_t*)0x40030050 )
245 #define GPTIMER0_TBV ( *(cc2538_reg_t*)0x40030054 )
246 #define GPTIMER0_TAPS ( *(cc2538_reg_t*)0x4003005c )
247 #define GPTIMER0_TBPS ( *(cc2538_reg_t*)0x40030060 )
248 #define GPTIMER0_TAPV ( *(cc2538_reg_t*)0x40030064 )
249 #define GPTIMER0_TBPV ( *(cc2538_reg_t*)0x40030068 )
250 #define GPTIMER0_PP ( *(cc2538_reg_t*)0x40030fc0 )
251 #define GPTIMER1_CFG ( *(cc2538_reg_t*)0x40031000 )
252 #define GPTIMER1_TAMR ( *(cc2538_reg_t*)0x40031004 )
253 #define GPTIMER1_TBMR ( *(cc2538_reg_t*)0x40031008 )
254 #define GPTIMER1_CTL ( *(cc2538_reg_t*)0x4003100c )
255 #define GPTIMER1_SYNC ( *(cc2538_reg_t*)0x40031010 )
256 #define GPTIMER1_IMR ( *(cc2538_reg_t*)0x40031018 )
257 #define GPTIMER1_RIS ( *(cc2538_reg_t*)0x4003101c )
258 #define GPTIMER1_MIS ( *(cc2538_reg_t*)0x40031020 )
259 #define GPTIMER1_ICR ( *(cc2538_reg_t*)0x40031024 )
260 #define GPTIMER1_TAILR ( *(cc2538_reg_t*)0x40031028 )
261 #define GPTIMER1_TBILR ( *(cc2538_reg_t*)0x4003102c )
262 #define GPTIMER1_TAMATCHR ( *(cc2538_reg_t*)0x40031030 )
263 #define GPTIMER1_TBMATCHR ( *(cc2538_reg_t*)0x40031034 )
264 #define GPTIMER1_TAPR ( *(cc2538_reg_t*)0x40031038 )
265 #define GPTIMER1_TBPR ( *(cc2538_reg_t*)0x4003103c )
266 #define GPTIMER1_TAPMR ( *(cc2538_reg_t*)0x40031040 )
267 #define GPTIMER1_TBPMR ( *(cc2538_reg_t*)0x40031044 )
268 #define GPTIMER1_TAR ( *(cc2538_reg_t*)0x40031048 )
269 #define GPTIMER1_TBR ( *(cc2538_reg_t*)0x4003104c )
270 #define GPTIMER1_TAV ( *(cc2538_reg_t*)0x40031050 )
271 #define GPTIMER1_TBV ( *(cc2538_reg_t*)0x40031054 )
272 #define GPTIMER1_TAPS ( *(cc2538_reg_t*)0x4003105c )
273 #define GPTIMER1_TBPS ( *(cc2538_reg_t*)0x40031060 )
274 #define GPTIMER1_TAPV ( *(cc2538_reg_t*)0x40031064 )
275 #define GPTIMER1_TBPV ( *(cc2538_reg_t*)0x40031068 )
276 #define GPTIMER1_PP ( *(cc2538_reg_t*)0x40031fc0 )
277 #define GPTIMER2_CFG ( *(cc2538_reg_t*)0x40032000 )
278 #define GPTIMER2_TAMR ( *(cc2538_reg_t*)0x40032004 )
279 #define GPTIMER2_TBMR ( *(cc2538_reg_t*)0x40032008 )
280 #define GPTIMER2_CTL ( *(cc2538_reg_t*)0x4003200c )
281 #define GPTIMER2_SYNC ( *(cc2538_reg_t*)0x40032010 )
282 #define GPTIMER2_IMR ( *(cc2538_reg_t*)0x40032018 )
283 #define GPTIMER2_RIS ( *(cc2538_reg_t*)0x4003201c )
284 #define GPTIMER2_MIS ( *(cc2538_reg_t*)0x40032020 )
285 #define GPTIMER2_ICR ( *(cc2538_reg_t*)0x40032024 )
286 #define GPTIMER2_TAILR ( *(cc2538_reg_t*)0x40032028 )
287 #define GPTIMER2_TBILR ( *(cc2538_reg_t*)0x4003202c )
288 #define GPTIMER2_TAMATCHR ( *(cc2538_reg_t*)0x40032030 )
289 #define GPTIMER2_TBMATCHR ( *(cc2538_reg_t*)0x40032034 )
290 #define GPTIMER2_TAPR ( *(cc2538_reg_t*)0x40032038 )
291 #define GPTIMER2_TBPR ( *(cc2538_reg_t*)0x4003203c )
292 #define GPTIMER2_TAPMR ( *(cc2538_reg_t*)0x40032040 )
293 #define GPTIMER2_TBPMR ( *(cc2538_reg_t*)0x40032044 )
294 #define GPTIMER2_TAR ( *(cc2538_reg_t*)0x40032048 )
295 #define GPTIMER2_TBR ( *(cc2538_reg_t*)0x4003204c )
296 #define GPTIMER2_TAV ( *(cc2538_reg_t*)0x40032050 )
297 #define GPTIMER2_TBV ( *(cc2538_reg_t*)0x40032054 )
298 #define GPTIMER2_TAPS ( *(cc2538_reg_t*)0x4003205c )
299 #define GPTIMER2_TBPS ( *(cc2538_reg_t*)0x40032060 )
300 #define GPTIMER2_TAPV ( *(cc2538_reg_t*)0x40032064 )
301 #define GPTIMER2_TBPV ( *(cc2538_reg_t*)0x40032068 )
302 #define GPTIMER2_PP ( *(cc2538_reg_t*)0x40032fc0 )
303 #define GPTIMER3_CFG ( *(cc2538_reg_t*)0x40033000 )
304 #define GPTIMER3_TAMR ( *(cc2538_reg_t*)0x40033004 )
305 #define GPTIMER3_TBMR ( *(cc2538_reg_t*)0x40033008 )
306 #define GPTIMER3_CTL ( *(cc2538_reg_t*)0x4003300c )
307 #define GPTIMER3_SYNC ( *(cc2538_reg_t*)0x40033010 )
308 #define GPTIMER3_IMR ( *(cc2538_reg_t*)0x40033018 )
309 #define GPTIMER3_RIS ( *(cc2538_reg_t*)0x4003301c )
310 #define GPTIMER3_MIS ( *(cc2538_reg_t*)0x40033020 )
311 #define GPTIMER3_ICR ( *(cc2538_reg_t*)0x40033024 )
312 #define GPTIMER3_TAILR ( *(cc2538_reg_t*)0x40033028 )
313 #define GPTIMER3_TBILR ( *(cc2538_reg_t*)0x4003302c )
314 #define GPTIMER3_TAMATCHR ( *(cc2538_reg_t*)0x40033030 )
315 #define GPTIMER3_TBMATCHR ( *(cc2538_reg_t*)0x40033034 )
316 #define GPTIMER3_TAPR ( *(cc2538_reg_t*)0x40033038 )
317 #define GPTIMER3_TBPR ( *(cc2538_reg_t*)0x4003303c )
318 #define GPTIMER3_TAPMR ( *(cc2538_reg_t*)0x40033040 )
319 #define GPTIMER3_TBPMR ( *(cc2538_reg_t*)0x40033044 )
320 #define GPTIMER3_TAR ( *(cc2538_reg_t*)0x40033048 )
321 #define GPTIMER3_TBR ( *(cc2538_reg_t*)0x4003304c )
322 #define GPTIMER3_TAV ( *(cc2538_reg_t*)0x40033050 )
323 #define GPTIMER3_TBV ( *(cc2538_reg_t*)0x40033054 )
324 #define GPTIMER3_TAPS ( *(cc2538_reg_t*)0x4003305c )
325 #define GPTIMER3_TBPS ( *(cc2538_reg_t*)0x40033060 )
326 #define GPTIMER3_TAPV ( *(cc2538_reg_t*)0x40033064 )
327 #define GPTIMER3_TBPV ( *(cc2538_reg_t*)0x40033068 )
328 #define GPTIMER3_PP ( *(cc2538_reg_t*)0x40033fc0 )
329 #define RFCORE_FFSM_SRCRESMASK0 ( *(cc2538_reg_t*)0x40088580 )
330 #define RFCORE_FFSM_SRCRESMASK1 ( *(cc2538_reg_t*)0x40088584 )
331 #define RFCORE_FFSM_SRCRESMASK2 ( *(cc2538_reg_t*)0x40088588 )
332 #define RFCORE_FFSM_SRCRESINDEX ( *(cc2538_reg_t*)0x4008858c )
333 #define RFCORE_FFSM_SRCEXTPENDEN0 ( *(cc2538_reg_t*)0x40088590 )
334 #define RFCORE_FFSM_SRCEXTPENDEN1 ( *(cc2538_reg_t*)0x40088594 )
335 #define RFCORE_FFSM_SRCEXTPENDEN2 ( *(cc2538_reg_t*)0x40088598 )
336 #define RFCORE_FFSM_SRCSHORTPENDEN0 ( *(cc2538_reg_t*)0x4008859c )
337 #define RFCORE_FFSM_SRCSHORTPENDEN1 ( *(cc2538_reg_t*)0x400885a0 )
338 #define RFCORE_FFSM_SRCSHORTPENDEN2 ( *(cc2538_reg_t*)0x400885a4 )
339 #define RFCORE_FFSM_EXT_ADDR0 ( *(cc2538_reg_t*)0x400885a8 )
340 #define RFCORE_FFSM_EXT_ADDR1 ( *(cc2538_reg_t*)0x400885ac )
341 #define RFCORE_FFSM_EXT_ADDR2 ( *(cc2538_reg_t*)0x400885b0 )
342 #define RFCORE_FFSM_EXT_ADDR3 ( *(cc2538_reg_t*)0x400885b4 )
343 #define RFCORE_FFSM_EXT_ADDR4 ( *(cc2538_reg_t*)0x400885b8 )
344 #define RFCORE_FFSM_EXT_ADDR5 ( *(cc2538_reg_t*)0x400885bc )
345 #define RFCORE_FFSM_EXT_ADDR6 ( *(cc2538_reg_t*)0x400885c0 )
346 #define RFCORE_FFSM_EXT_ADDR7 ( *(cc2538_reg_t*)0x400885c4 )
347 #define RFCORE_FFSM_PAN_ID0 ( *(cc2538_reg_t*)0x400885c8 )
348 #define RFCORE_FFSM_PAN_ID1 ( *(cc2538_reg_t*)0x400885cc )
349 #define RFCORE_FFSM_SHORT_ADDR0 ( *(cc2538_reg_t*)0x400885d0 )
350 #define RFCORE_FFSM_SHORT_ADDR1 ( *(cc2538_reg_t*)0x400885d4 )
351 #define RFCORE_XREG_FRMFILT0 ( *(cc2538_reg_t*)0x40088600 )
352 #define RFCORE_XREG_FRMFILT1 ( *(cc2538_reg_t*)0x40088604 )
353 #define RFCORE_XREG_SRCMATCH ( *(cc2538_reg_t*)0x40088608 )
354 #define RFCORE_XREG_SRCSHORTEN0 ( *(cc2538_reg_t*)0x4008860c )
355 #define RFCORE_XREG_SRCSHORTEN1 ( *(cc2538_reg_t*)0x40088610 )
356 #define RFCORE_XREG_SRCSHORTEN2 ( *(cc2538_reg_t*)0x40088614 )
357 #define RFCORE_XREG_SRCEXTEN0 ( *(cc2538_reg_t*)0x40088618 )
358 #define RFCORE_XREG_SRCEXTEN1 ( *(cc2538_reg_t*)0x4008861c )
359 #define RFCORE_XREG_SRCEXTEN2 ( *(cc2538_reg_t*)0x40088620 )
360 #define RFCORE_XREG_FRMCTRL0 ( *(cc2538_reg_t*)0x40088624 )
361 #define RFCORE_XREG_FRMCTRL1 ( *(cc2538_reg_t*)0x40088628 )
362 #define RFCORE_XREG_RXENABLE ( *(cc2538_reg_t*)0x4008862c )
363 #define RFCORE_XREG_RXMASKSET ( *(cc2538_reg_t*)0x40088630 )
364 #define RFCORE_XREG_RXMASKCLR ( *(cc2538_reg_t*)0x40088634 )
365 #define RFCORE_XREG_FREQTUNE ( *(cc2538_reg_t*)0x40088638 )
366 #define RFCORE_XREG_FREQCTRL ( *(cc2538_reg_t*)0x4008863c )
367 #define RFCORE_XREG_TXPOWER ( *(cc2538_reg_t*)0x40088640 )
368 #define RFCORE_XREG_TXCTRL ( *(cc2538_reg_t*)0x40088644 )
369 #define RFCORE_XREG_FSMSTAT0 ( *(cc2538_reg_t*)0x40088648 )
370 #define RFCORE_XREG_FSMSTAT1 ( *(cc2538_reg_t*)0x4008864c )
371 #define RFCORE_XREG_FIFOPCTRL ( *(cc2538_reg_t*)0x40088650 )
372 #define RFCORE_XREG_FSMCTRL ( *(cc2538_reg_t*)0x40088654 )
373 #define RFCORE_XREG_CCACTRL0 ( *(cc2538_reg_t*)0x40088658 )
374 #define RFCORE_XREG_CCACTRL1 ( *(cc2538_reg_t*)0x4008865c )
375 #define RFCORE_XREG_RSSI ( *(cc2538_reg_t*)0x40088660 )
376 #define RFCORE_XREG_RSSISTAT ( *(cc2538_reg_t*)0x40088664 )
377 #define RFCORE_XREG_RXFIRST ( *(cc2538_reg_t*)0x40088668 )
378 #define RFCORE_XREG_RXFIFOCNT ( *(cc2538_reg_t*)0x4008866c )
379 #define RFCORE_XREG_TXFIFOCNT ( *(cc2538_reg_t*)0x40088670 )
380 #define RFCORE_XREG_RXFIRST_PTR ( *(cc2538_reg_t*)0x40088674 )
381 #define RFCORE_XREG_RXLAST_PTR ( *(cc2538_reg_t*)0x40088678 )
382 #define RFCORE_XREG_RXP1_PTR ( *(cc2538_reg_t*)0x4008867c )
383 #define RFCORE_XREG_TXFIRST_PTR ( *(cc2538_reg_t*)0x40088684 )
384 #define RFCORE_XREG_TXLAST_PTR ( *(cc2538_reg_t*)0x40088688 )
385 #define RFCORE_XREG_RFIRQM0 ( *(cc2538_reg_t*)0x4008868c )
386 #define RFCORE_XREG_RFIRQM1 ( *(cc2538_reg_t*)0x40088690 )
387 #define RFCORE_XREG_RFERRM ( *(cc2538_reg_t*)0x40088694 )
388 #define RFCORE_XREG_RFRND ( *(cc2538_reg_t*)0x4008869c )
389 #define RFCORE_XREG_MDMCTRL0 ( *(cc2538_reg_t*)0x400886a0 )
390 #define RFCORE_XREG_MDMCTRL1 ( *(cc2538_reg_t*)0x400886a4 )
391 #define RFCORE_XREG_FREQEST ( *(cc2538_reg_t*)0x400886a8 )
392 #define RFCORE_XREG_RXCTRL ( *(cc2538_reg_t*)0x400886ac )
393 #define RFCORE_XREG_FSCTRL ( *(cc2538_reg_t*)0x400886b0 )
394 #define RFCORE_XREG_FSCAL0 ( *(cc2538_reg_t*)0x400886b4 )
395 #define RFCORE_XREG_FSCAL1 ( *(cc2538_reg_t*)0x400886b8 )
396 #define RFCORE_XREG_FSCAL2 ( *(cc2538_reg_t*)0x400886bc )
397 #define RFCORE_XREG_FSCAL3 ( *(cc2538_reg_t*)0x400886c0 )
398 #define RFCORE_XREG_AGCCTRL0 ( *(cc2538_reg_t*)0x400886c4 )
399 #define RFCORE_XREG_AGCCTRL1 ( *(cc2538_reg_t*)0x400886c8 )
400 #define RFCORE_XREG_AGCCTRL2 ( *(cc2538_reg_t*)0x400886cc )
401 #define RFCORE_XREG_AGCCTRL3 ( *(cc2538_reg_t*)0x400886d0 )
402 #define RFCORE_XREG_ADCTEST0 ( *(cc2538_reg_t*)0x400886d4 )
403 #define RFCORE_XREG_ADCTEST1 ( *(cc2538_reg_t*)0x400886d8 )
404 #define RFCORE_XREG_ADCTEST2 ( *(cc2538_reg_t*)0x400886dc )
405 #define RFCORE_XREG_MDMTEST0 ( *(cc2538_reg_t*)0x400886e0 )
406 #define RFCORE_XREG_MDMTEST1 ( *(cc2538_reg_t*)0x400886e4 )
407 #define RFCORE_XREG_DACTEST0 ( *(cc2538_reg_t*)0x400886e8 )
408 #define RFCORE_XREG_DACTEST1 ( *(cc2538_reg_t*)0x400886ec )
409 #define RFCORE_XREG_DACTEST2 ( *(cc2538_reg_t*)0x400886f0 )
410 #define RFCORE_XREG_ATEST ( *(cc2538_reg_t*)0x400886f4 )
411 #define RFCORE_XREG_PTEST0 ( *(cc2538_reg_t*)0x400886f8 )
412 #define RFCORE_XREG_PTEST1 ( *(cc2538_reg_t*)0x400886fc )
413 #define RFCORE_XREG_CSPCTRL ( *(cc2538_reg_t*)0x40088780 )
414 #define RFCORE_XREG_CSPSTAT ( *(cc2538_reg_t*)0x40088784 )
415 #define RFCORE_XREG_CSPX ( *(cc2538_reg_t*)0x40088788 )
416 #define RFCORE_XREG_CSPY ( *(cc2538_reg_t*)0x4008878c )
417 #define RFCORE_XREG_CSPZ ( *(cc2538_reg_t*)0x40088790 )
418 #define RFCORE_XREG_CSPT ( *(cc2538_reg_t*)0x40088794 )
419 #define RFCORE_XREG_RFC_OBS_CTRL0 ( *(cc2538_reg_t*)0x400887ac )
420 #define RFCORE_XREG_RFC_OBS_CTRL1 ( *(cc2538_reg_t*)0x400887b0 )
421 #define RFCORE_XREG_RFC_OBS_CTRL2 ( *(cc2538_reg_t*)0x400887b4 )
422 #define RFCORE_XREG_TXFILTCFG ( *(cc2538_reg_t*)0x400887e8 )
423 #define RFCORE_SFR_MTCSPCFG ( *(cc2538_reg_t*)0x40088800 )
424 #define RFCORE_SFR_MTCTRL ( *(cc2538_reg_t*)0x40088804 )
425 #define RFCORE_SFR_MTIRQM ( *(cc2538_reg_t*)0x40088808 )
426 #define RFCORE_SFR_MTIRQF ( *(cc2538_reg_t*)0x4008880c )
427 #define RFCORE_SFR_MTMSEL ( *(cc2538_reg_t*)0x40088810 )
428 #define RFCORE_SFR_MTM0 ( *(cc2538_reg_t*)0x40088814 )
429 #define RFCORE_SFR_MTM1 ( *(cc2538_reg_t*)0x40088818 )
430 #define RFCORE_SFR_MTMOVF2 ( *(cc2538_reg_t*)0x4008881c )
431 #define RFCORE_SFR_MTMOVF1 ( *(cc2538_reg_t*)0x40088820 )
432 #define RFCORE_SFR_MTMOVF0 ( *(cc2538_reg_t*)0x40088824 )
433 #define RFCORE_SFR_RFDATA ( *(cc2538_reg_t*)0x40088828 )
434 #define RFCORE_SFR_RFERRF ( *(cc2538_reg_t*)0x4008882c )
435 #define RFCORE_SFR_RFIRQF1 ( *(cc2538_reg_t*)0x40088830 )
436 #define RFCORE_SFR_RFIRQF0 ( *(cc2538_reg_t*)0x40088834 )
437 #define RFCORE_SFR_RFST ( *(cc2538_reg_t*)0x40088838 )
438 #define USB_ADDR ( *(cc2538_reg_t*)0x40089000 )
439 #define USB_POW ( *(cc2538_reg_t*)0x40089004 )
440 #define USB_IIF ( *(cc2538_reg_t*)0x40089008 )
441 #define USB_OIF ( *(cc2538_reg_t*)0x40089010 )
442 #define USB_CIF ( *(cc2538_reg_t*)0x40089018 )
443 #define USB_IIE ( *(cc2538_reg_t*)0x4008901c )
444 #define USB_OIE ( *(cc2538_reg_t*)0x40089024 )
445 #define USB_CIE ( *(cc2538_reg_t*)0x4008902c )
446 #define USB_FRML ( *(cc2538_reg_t*)0x40089030 )
447 #define USB_FRMH ( *(cc2538_reg_t*)0x40089034 )
448 #define USB_INDEX ( *(cc2538_reg_t*)0x40089038 )
449 #define USB_CTRL ( *(cc2538_reg_t*)0x4008903c )
450 #define USB_MAXI ( *(cc2538_reg_t*)0x40089040 )
451 #define USB_CS0_CSIL ( *(cc2538_reg_t*)0x40089044 )
452 #define USB_CSIH ( *(cc2538_reg_t*)0x40089048 )
453 #define USB_MAXO ( *(cc2538_reg_t*)0x4008904c )
454 #define USB_CSOL ( *(cc2538_reg_t*)0x40089050 )
455 #define USB_CSOH ( *(cc2538_reg_t*)0x40089054 )
456 #define USB_CNT0_CNTL ( *(cc2538_reg_t*)0x40089058 )
457 #define USB_CNTH ( *(cc2538_reg_t*)0x4008905c )
458 #define USB_F0 ( *(cc2538_reg_t*)0x40089080 )
459 #define USB_F1 ( *(cc2538_reg_t*)0x40089088 )
460 #define USB_F2 ( *(cc2538_reg_t*)0x40089090 )
461 #define USB_F3 ( *(cc2538_reg_t*)0x40089098 )
462 #define USB_F4 ( *(cc2538_reg_t*)0x400890a0 )
463 #define USB_F5 ( *(cc2538_reg_t*)0x400890a8 )
464 #define AES_DMAC_CH0_CTRL ( *(cc2538_reg_t*)0x4008b000 )
465 #define AES_DMAC_CH0_EXTADDR ( *(cc2538_reg_t*)0x4008b004 )
466 #define AES_DMAC_CH0_DMALENGTH ( *(cc2538_reg_t*)0x4008b00c )
467 #define AES_DMAC_STATUS ( *(cc2538_reg_t*)0x4008b018 )
468 #define AES_DMAC_SWRES ( *(cc2538_reg_t*)0x4008b01c )
469 #define AES_DMAC_CH1_CTRL ( *(cc2538_reg_t*)0x4008b020 )
470 #define AES_DMAC_CH1_EXTADDR ( *(cc2538_reg_t*)0x4008b024 )
471 #define AES_DMAC_CH1_DMALENGTH ( *(cc2538_reg_t*)0x4008b02c )
472 #define AES_DMAC_MST_RUNPARAMS ( *(cc2538_reg_t*)0x4008b078 )
473 #define AES_DMAC_PERSR ( *(cc2538_reg_t*)0x4008b07c )
474 #define AES_DMAC_OPTIONS ( *(cc2538_reg_t*)0x4008b0f8 )
475 #define AES_DMAC_VERSION ( *(cc2538_reg_t*)0x4008b0fc )
476 #define AES_KEY_STORE_WRITE_AREA ( *(cc2538_reg_t*)0x4008b400 )
477 #define AES_KEY_STORE_WRITTEN_AREA ( *(cc2538_reg_t*)0x4008b404 )
478 #define AES_KEY_STORE_SIZE ( *(cc2538_reg_t*)0x4008b408 )
479 #define AES_KEY_STORE_READ_AREA ( *(cc2538_reg_t*)0x4008b40c )
480 #define AES_AES_KEY2_0 ( *(cc2538_reg_t*)0x4008b500 )
481 #define AES_AES_KEY2_1 ( *(cc2538_reg_t*)0x4008b504 )
482 #define AES_AES_KEY2_2 ( *(cc2538_reg_t*)0x4008b508 )
483 #define AES_AES_KEY2_3 ( *(cc2538_reg_t*)0x4008b50c )
484 #define AES_AES_KEY3_0 ( *(cc2538_reg_t*)0x4008b510 )
485 #define AES_AES_KEY3_1 ( *(cc2538_reg_t*)0x4008b514 )
486 #define AES_AES_KEY3_2 ( *(cc2538_reg_t*)0x4008b518 )
487 #define AES_AES_KEY3_3 ( *(cc2538_reg_t*)0x4008b51c )
488 #define AES_AES_IV_0 ( *(cc2538_reg_t*)0x4008b540 )
489 #define AES_AES_IV_1 ( *(cc2538_reg_t*)0x4008b544 )
490 #define AES_AES_IV_2 ( *(cc2538_reg_t*)0x4008b548 )
491 #define AES_AES_IV_3 ( *(cc2538_reg_t*)0x4008b54c )
492 #define AES_AES_CTRL ( *(cc2538_reg_t*)0x4008b550 )
493 #define AES_AES_C_LENGTH_0 ( *(cc2538_reg_t*)0x4008b554 )
494 #define AES_AES_C_LENGTH_1 ( *(cc2538_reg_t*)0x4008b558 )
495 #define AES_AES_AUTH_LENGTH ( *(cc2538_reg_t*)0x4008b55c )
496 #define AES_AES_DATA_IN_OUT_0 ( *(cc2538_reg_t*)0x4008b560 )
497 #define AES_AES_DATA_IN_OUT_1 ( *(cc2538_reg_t*)0x4008b564 )
498 #define AES_AES_DATA_IN_OUT_2 ( *(cc2538_reg_t*)0x4008b568 )
499 #define AES_AES_DATA_IN_OUT_3 ( *(cc2538_reg_t*)0x4008b56c )
500 #define AES_AES_TAG_OUT_0 ( *(cc2538_reg_t*)0x4008b570 )
501 #define AES_AES_TAG_OUT_1 ( *(cc2538_reg_t*)0x4008b574 )
502 #define AES_AES_TAG_OUT_2 ( *(cc2538_reg_t*)0x4008b578 )
503 #define AES_AES_TAG_OUT_3 ( *(cc2538_reg_t*)0x4008b57c )
504 #define AES_HASH_DATA_IN_0 ( *(cc2538_reg_t*)0x4008b600 )
505 #define AES_HASH_DATA_IN_1 ( *(cc2538_reg_t*)0x4008b604 )
506 #define AES_HASH_DATA_IN_2 ( *(cc2538_reg_t*)0x4008b608 )
507 #define AES_HASH_DATA_IN_3 ( *(cc2538_reg_t*)0x4008b60c )
508 #define AES_HASH_DATA_IN_4 ( *(cc2538_reg_t*)0x4008b610 )
509 #define AES_HASH_DATA_IN_5 ( *(cc2538_reg_t*)0x4008b614 )
510 #define AES_HASH_DATA_IN_6 ( *(cc2538_reg_t*)0x4008b618 )
511 #define AES_HASH_DATA_IN_7 ( *(cc2538_reg_t*)0x4008b61c )
512 #define AES_HASH_DATA_IN_8 ( *(cc2538_reg_t*)0x4008b620 )
513 #define AES_HASH_DATA_IN_9 ( *(cc2538_reg_t*)0x4008b624 )
514 #define AES_HASH_DATA_IN_10 ( *(cc2538_reg_t*)0x4008b628 )
515 #define AES_HASH_DATA_IN_11 ( *(cc2538_reg_t*)0x4008b62c )
516 #define AES_HASH_DATA_IN_12 ( *(cc2538_reg_t*)0x4008b630 )
517 #define AES_HASH_DATA_IN_13 ( *(cc2538_reg_t*)0x4008b634 )
518 #define AES_HASH_DATA_IN_14 ( *(cc2538_reg_t*)0x4008b638 )
519 #define AES_HASH_DATA_IN_15 ( *(cc2538_reg_t*)0x4008b63c )
520 #define AES_HASH_IO_BUF_CTRL ( *(cc2538_reg_t*)0x4008b640 )
521 #define AES_HASH_MODE_IN ( *(cc2538_reg_t*)0x4008b644 )
522 #define AES_HASH_LENGTH_IN_L ( *(cc2538_reg_t*)0x4008b648 )
523 #define AES_HASH_LENGTH_IN_H ( *(cc2538_reg_t*)0x4008b64c )
524 #define AES_HASH_DIGEST_A ( *(cc2538_reg_t*)0x4008b650 )
525 #define AES_HASH_DIGEST_B ( *(cc2538_reg_t*)0x4008b654 )
526 #define AES_HASH_DIGEST_C ( *(cc2538_reg_t*)0x4008b658 )
527 #define AES_HASH_DIGEST_D ( *(cc2538_reg_t*)0x4008b65c )
528 #define AES_HASH_DIGEST_E ( *(cc2538_reg_t*)0x4008b660 )
529 #define AES_HASH_DIGEST_F ( *(cc2538_reg_t*)0x4008b664 )
530 #define AES_HASH_DIGEST_G ( *(cc2538_reg_t*)0x4008b668 )
531 #define AES_HASH_DIGEST_H ( *(cc2538_reg_t*)0x4008b66c )
532 #define AES_CTRL_ALG_SEL ( *(cc2538_reg_t*)0x4008b700 )
533 #define AES_CTRL_PROT_EN ( *(cc2538_reg_t*)0x4008b704 )
534 #define AES_CTRL_SW_RESET ( *(cc2538_reg_t*)0x4008b740 )
535 #define AES_CTRL_INT_CFG ( *(cc2538_reg_t*)0x4008b780 )
536 #define AES_CTRL_INT_EN ( *(cc2538_reg_t*)0x4008b784 )
537 #define AES_CTRL_INT_CLR ( *(cc2538_reg_t*)0x4008b788 )
538 #define AES_CTRL_INT_SET ( *(cc2538_reg_t*)0x4008b78c )
539 #define AES_CTRL_INT_STAT ( *(cc2538_reg_t*)0x4008b790 )
540 #define AES_CTRL_OPTIONS ( *(cc2538_reg_t*)0x4008b7f8 )
541 #define AES_CTRL_VERSION ( *(cc2538_reg_t*)0x4008b7fc )
542 #define SYS_CTRL_CLOCK_CTRL ( *(cc2538_reg_t*)0x400d2000 )
543 #define SYS_CTRL_CLOCK_STA ( *(cc2538_reg_t*)0x400d2004 )
544 #define SYS_CTRL_RCGCGPT ( *(cc2538_reg_t*)0x400d2008 )
545 #define SYS_CTRL_SCGCGPT ( *(cc2538_reg_t*)0x400d200c )
546 #define SYS_CTRL_DCGCGPT ( *(cc2538_reg_t*)0x400d2010 )
547 #define SYS_CTRL_SRGPT ( *(cc2538_reg_t*)0x400d2014 )
548 #define SYS_CTRL_RCGCSSI ( *(cc2538_reg_t*)0x400d2018 )
549 #define SYS_CTRL_SCGCSSI ( *(cc2538_reg_t*)0x400d201c )
550 #define SYS_CTRL_DCGCSSI ( *(cc2538_reg_t*)0x400d2020 )
551 #define SYS_CTRL_SRSSI ( *(cc2538_reg_t*)0x400d2024 )
552 #define SYS_CTRL_RCGCUART ( *(cc2538_reg_t*)0x400d2028 )
553 #define SYS_CTRL_SCGCUART ( *(cc2538_reg_t*)0x400d202c )
554 #define SYS_CTRL_DCGCUART ( *(cc2538_reg_t*)0x400d2030 )
555 #define SYS_CTRL_SRUART ( *(cc2538_reg_t*)0x400d2034 )
556 #define SYS_CTRL_RCGCI2C ( *(cc2538_reg_t*)0x400d2038 )
557 #define SYS_CTRL_SCGCI2C ( *(cc2538_reg_t*)0x400d203c )
558 #define SYS_CTRL_DCGCI2C ( *(cc2538_reg_t*)0x400d2040 )
559 #define SYS_CTRL_SRI2C ( *(cc2538_reg_t*)0x400d2044 )
560 #define SYS_CTRL_RCGCSEC ( *(cc2538_reg_t*)0x400d2048 )
561 #define SYS_CTRL_SCGCSEC ( *(cc2538_reg_t*)0x400d204c )
562 #define SYS_CTRL_DCGCSEC ( *(cc2538_reg_t*)0x400d2050 )
563 #define SYS_CTRL_SRSEC ( *(cc2538_reg_t*)0x400d2054 )
564 #define SYS_CTRL_PMCTL ( *(cc2538_reg_t*)0x400d2058 )
565 #define SYS_CTRL_SRCRC ( *(cc2538_reg_t*)0x400d205c )
566 #define SYS_CTRL_PWRDBG ( *(cc2538_reg_t*)0x400d2074 )
567 #define SYS_CTRL_CLD ( *(cc2538_reg_t*)0x400d2080 )
568 #define SYS_CTRL_IWE ( *(cc2538_reg_t*)0x400d2094 )
569 #define SYS_CTRL_I_MAP ( *(cc2538_reg_t*)0x400d2098 )
570 #define SYS_CTRL_RCGCRFC ( *(cc2538_reg_t*)0x400d20a8 )
571 #define SYS_CTRL_SCGCRFC ( *(cc2538_reg_t*)0x400d20ac )
572 #define SYS_CTRL_DCGCRFC ( *(cc2538_reg_t*)0x400d20b0 )
573 #define SYS_CTRL_EMUOVR ( *(cc2538_reg_t*)0x400d20b4 )
574 #define FLASH_CTRL_FCTL ( *(cc2538_reg_t*)0x400d3008 )
575 #define FLASH_CTRL_FADDR ( *(cc2538_reg_t*)0x400d300c )
576 #define FLASH_CTRL_FWDATA ( *(cc2538_reg_t*)0x400d3010 )
577 #define FLASH_CTRL_DIECFG0 ( *(cc2538_reg_t*)0x400d3014 )
578 #define FLASH_CTRL_DIECFG1 ( *(cc2538_reg_t*)0x400d3018 )
579 #define FLASH_CTRL_DIECFG2 ( *(cc2538_reg_t*)0x400d301c )
580 #define IOC_PA0_SEL ( *(cc2538_reg_t*)0x400d4000 )
581 #define IOC_PA1_SEL ( *(cc2538_reg_t*)0x400d4004 )
582 #define IOC_PA2_SEL ( *(cc2538_reg_t*)0x400d4008 )
583 #define IOC_PA3_SEL ( *(cc2538_reg_t*)0x400d400c )
584 #define IOC_PA4_SEL ( *(cc2538_reg_t*)0x400d4010 )
585 #define IOC_PA5_SEL ( *(cc2538_reg_t*)0x400d4014 )
586 #define IOC_PA6_SEL ( *(cc2538_reg_t*)0x400d4018 )
587 #define IOC_PA7_SEL ( *(cc2538_reg_t*)0x400d401c )
588 #define IOC_PB0_SEL ( *(cc2538_reg_t*)0x400d4020 )
589 #define IOC_PB1_SEL ( *(cc2538_reg_t*)0x400d4024 )
590 #define IOC_PB2_SEL ( *(cc2538_reg_t*)0x400d4028 )
591 #define IOC_PB3_SEL ( *(cc2538_reg_t*)0x400d402c )
592 #define IOC_PB4_SEL ( *(cc2538_reg_t*)0x400d4030 )
593 #define IOC_PB5_SEL ( *(cc2538_reg_t*)0x400d4034 )
594 #define IOC_PB6_SEL ( *(cc2538_reg_t*)0x400d4038 )
595 #define IOC_PB7_SEL ( *(cc2538_reg_t*)0x400d403c )
596 #define IOC_PC0_SEL ( *(cc2538_reg_t*)0x400d4040 )
597 #define IOC_PC1_SEL ( *(cc2538_reg_t*)0x400d4044 )
598 #define IOC_PC2_SEL ( *(cc2538_reg_t*)0x400d4048 )
599 #define IOC_PC3_SEL ( *(cc2538_reg_t*)0x400d404c )
600 #define IOC_PC4_SEL ( *(cc2538_reg_t*)0x400d4050 )
601 #define IOC_PC5_SEL ( *(cc2538_reg_t*)0x400d4054 )
602 #define IOC_PC6_SEL ( *(cc2538_reg_t*)0x400d4058 )
603 #define IOC_PC7_SEL ( *(cc2538_reg_t*)0x400d405c )
604 #define IOC_PD0_SEL ( *(cc2538_reg_t*)0x400d4060 )
605 #define IOC_PD1_SEL ( *(cc2538_reg_t*)0x400d4064 )
606 #define IOC_PD2_SEL ( *(cc2538_reg_t*)0x400d4068 )
607 #define IOC_PD3_SEL ( *(cc2538_reg_t*)0x400d406c )
608 #define IOC_PD4_SEL ( *(cc2538_reg_t*)0x400d4070 )
609 #define IOC_PD5_SEL ( *(cc2538_reg_t*)0x400d4074 )
610 #define IOC_PD6_SEL ( *(cc2538_reg_t*)0x400d4078 )
611 #define IOC_PD7_SEL ( *(cc2538_reg_t*)0x400d407c )
612 #define IOC_PA0_OVER ( *(cc2538_reg_t*)0x400d4080 )
613 #define IOC_PA1_OVER ( *(cc2538_reg_t*)0x400d4084 )
614 #define IOC_PA2_OVER ( *(cc2538_reg_t*)0x400d4088 )
615 #define IOC_PA3_OVER ( *(cc2538_reg_t*)0x400d408c )
616 #define IOC_PA4_OVER ( *(cc2538_reg_t*)0x400d4090 )
617 #define IOC_PA5_OVER ( *(cc2538_reg_t*)0x400d4094 )
618 #define IOC_PA6_OVER ( *(cc2538_reg_t*)0x400d4098 )
619 #define IOC_PA7_OVER ( *(cc2538_reg_t*)0x400d409c )
620 #define IOC_PB0_OVER ( *(cc2538_reg_t*)0x400d40a0 )
621 #define IOC_PB1_OVER ( *(cc2538_reg_t*)0x400d40a4 )
622 #define IOC_PB2_OVER ( *(cc2538_reg_t*)0x400d40a8 )
623 #define IOC_PB3_OVER ( *(cc2538_reg_t*)0x400d40ac )
624 #define IOC_PB4_OVER ( *(cc2538_reg_t*)0x400d40b0 )
625 #define IOC_PB5_OVER ( *(cc2538_reg_t*)0x400d40b4 )
626 #define IOC_PB6_OVER ( *(cc2538_reg_t*)0x400d40b8 )
627 #define IOC_PB7_OVER ( *(cc2538_reg_t*)0x400d40bc )
628 #define IOC_PC0_OVER ( *(cc2538_reg_t*)0x400d40c0 )
629 #define IOC_PC1_OVER ( *(cc2538_reg_t*)0x400d40c4 )
630 #define IOC_PC2_OVER ( *(cc2538_reg_t*)0x400d40c8 )
631 #define IOC_PC3_OVER ( *(cc2538_reg_t*)0x400d40cc )
632 #define IOC_PC4_OVER ( *(cc2538_reg_t*)0x400d40d0 )
633 #define IOC_PC5_OVER ( *(cc2538_reg_t*)0x400d40d4 )
634 #define IOC_PC6_OVER ( *(cc2538_reg_t*)0x400d40d8 )
635 #define IOC_PC7_OVER ( *(cc2538_reg_t*)0x400d40dc )
636 #define IOC_PD0_OVER ( *(cc2538_reg_t*)0x400d40e0 )
637 #define IOC_PD1_OVER ( *(cc2538_reg_t*)0x400d40e4 )
638 #define IOC_PD2_OVER ( *(cc2538_reg_t*)0x400d40e8 )
639 #define IOC_PD3_OVER ( *(cc2538_reg_t*)0x400d40ec )
640 #define IOC_PD4_OVER ( *(cc2538_reg_t*)0x400d40f0 )
641 #define IOC_PD5_OVER ( *(cc2538_reg_t*)0x400d40f4 )
642 #define IOC_PD6_OVER ( *(cc2538_reg_t*)0x400d40f8 )
643 #define IOC_PD7_OVER ( *(cc2538_reg_t*)0x400d40fc )
644 #define IOC_UARTRXD_UART0 ( *(cc2538_reg_t*)0x400d4100 )
645 #define IOC_UARTCTS_UART1 ( *(cc2538_reg_t*)0x400d4104 )
646 #define IOC_UARTRXD_UART1 ( *(cc2538_reg_t*)0x400d4108 )
647 #define IOC_CLK_SSI_SSI0 ( *(cc2538_reg_t*)0x400d410c )
648 #define IOC_SSIRXD_SSI0 ( *(cc2538_reg_t*)0x400d4110 )
649 #define IOC_SSIFSSIN_SSI0 ( *(cc2538_reg_t*)0x400d4114 )
650 #define IOC_CLK_SSIIN_SSI0 ( *(cc2538_reg_t*)0x400d4118 )
651 #define IOC_CLK_SSI_SSI1 ( *(cc2538_reg_t*)0x400d411c )
652 #define IOC_SSIRXD_SSI1 ( *(cc2538_reg_t*)0x400d4120 )
653 #define IOC_SSIFSSIN_SSI1 ( *(cc2538_reg_t*)0x400d4124 )
654 #define IOC_CLK_SSIIN_SSI1 ( *(cc2538_reg_t*)0x400d4128 )
655 #define IOC_I2CMSSDA ( *(cc2538_reg_t*)0x400d412c )
656 #define IOC_I2CMSSCL ( *(cc2538_reg_t*)0x400d4130 )
657 #define IOC_GPT0OCP1 ( *(cc2538_reg_t*)0x400d4134 )
658 #define IOC_GPT0OCP2 ( *(cc2538_reg_t*)0x400d4138 )
659 #define IOC_GPT1OCP1 ( *(cc2538_reg_t*)0x400d413c )
660 #define IOC_GPT1OCP2 ( *(cc2538_reg_t*)0x400d4140 )
661 #define IOC_GPT2OCP1 ( *(cc2538_reg_t*)0x400d4144 )
662 #define IOC_GPT2OCP2 ( *(cc2538_reg_t*)0x400d4148 )
663 #define IOC_GPT3OCP1 ( *(cc2538_reg_t*)0x400d414c )
664 #define IOC_GPT3OCP2 ( *(cc2538_reg_t*)0x400d4150 )
665 #define SMWDTHROSC_WDCTL ( *(cc2538_reg_t*)0x400d5000 )
666 #define SMWDTHROSC_ST0 ( *(cc2538_reg_t*)0x400d5040 )
667 #define SMWDTHROSC_ST1 ( *(cc2538_reg_t*)0x400d5044 )
668 #define SMWDTHROSC_ST2 ( *(cc2538_reg_t*)0x400d5048 )
669 #define SMWDTHROSC_ST3 ( *(cc2538_reg_t*)0x400d504c )
670 #define SMWDTHROSC_STLOAD ( *(cc2538_reg_t*)0x400d5050 )
671 #define SMWDTHROSC_STCC ( *(cc2538_reg_t*)0x400d5054 )
672 #define SMWDTHROSC_STCS ( *(cc2538_reg_t*)0x400d5058 )
673 #define SMWDTHROSC_STCV0 ( *(cc2538_reg_t*)0x400d505c )
674 #define SMWDTHROSC_STCV1 ( *(cc2538_reg_t*)0x400d5060 )
675 #define SMWDTHROSC_STCV2 ( *(cc2538_reg_t*)0x400d5064 )
676 #define SMWDTHROSC_STCV3 ( *(cc2538_reg_t*)0x400d5068 )
677 #define ANA_REGS_IVCTRL ( *(cc2538_reg_t*)0x400d6004 )
678 #define SOC_ADC_ADCCON1 ( *(cc2538_reg_t*)0x400d7000 )
679 #define SOC_ADC_ADCCON2 ( *(cc2538_reg_t*)0x400d7004 )
680 #define SOC_ADC_ADCCON3 ( *(cc2538_reg_t*)0x400d7008 )
681 #define SOC_ADC_ADCL ( *(cc2538_reg_t*)0x400d700c )
682 #define SOC_ADC_ADCH ( *(cc2538_reg_t*)0x400d7010 )
683 #define SOC_ADC_RNDL ( *(cc2538_reg_t*)0x400d7014 )
684 #define SOC_ADC_RNDH ( *(cc2538_reg_t*)0x400d7018 )
685 #define SOC_ADC_CMPCTL ( *(cc2538_reg_t*)0x400d7024 )
686 #define GPIO_A_DATA ( *(cc2538_reg_t*)0x400d9000 )
687 #define GPIO_A_DIR ( *(cc2538_reg_t*)0x400d9400 )
688 #define GPIO_A_IS ( *(cc2538_reg_t*)0x400d9404 )
689 #define GPIO_A_IBE ( *(cc2538_reg_t*)0x400d9408 )
690 #define GPIO_A_IEV ( *(cc2538_reg_t*)0x400d940c )
691 #define GPIO_A_IE ( *(cc2538_reg_t*)0x400d9410 )
692 #define GPIO_A_RIS ( *(cc2538_reg_t*)0x400d9414 )
693 #define GPIO_A_MIS ( *(cc2538_reg_t*)0x400d9418 )
694 #define GPIO_A_IC ( *(cc2538_reg_t*)0x400d941c )
695 #define GPIO_A_AFSEL ( *(cc2538_reg_t*)0x400d9420 )
696 #define GPIO_A_GPIOLOCK ( *(cc2538_reg_t*)0x400d9520 )
697 #define GPIO_A_GPIOCR ( *(cc2538_reg_t*)0x400d9524 )
698 #define GPIO_A_PMUX ( *(cc2538_reg_t*)0x400d9700 )
699 #define GPIO_A_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400d9704 )
700 #define GPIO_A_PI_IEN ( *(cc2538_reg_t*)0x400d9710 )
701 #define GPIO_A_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400d9718 )
702 #define GPIO_A_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400d971c )
703 #define GPIO_A_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400d9720 )
704 #define GPIO_B_DATA ( *(cc2538_reg_t*)0x400da000 )
705 #define GPIO_B_DIR ( *(cc2538_reg_t*)0x400da400 )
706 #define GPIO_B_IS ( *(cc2538_reg_t*)0x400da404 )
707 #define GPIO_B_IBE ( *(cc2538_reg_t*)0x400da408 )
708 #define GPIO_B_IEV ( *(cc2538_reg_t*)0x400da40c )
709 #define GPIO_B_IE ( *(cc2538_reg_t*)0x400da410 )
710 #define GPIO_B_RIS ( *(cc2538_reg_t*)0x400da414 )
711 #define GPIO_B_MIS ( *(cc2538_reg_t*)0x400da418 )
712 #define GPIO_B_IC ( *(cc2538_reg_t*)0x400da41c )
713 #define GPIO_B_AFSEL ( *(cc2538_reg_t*)0x400da420 )
714 #define GPIO_B_GPIOLOCK ( *(cc2538_reg_t*)0x400da520 )
715 #define GPIO_B_GPIOCR ( *(cc2538_reg_t*)0x400da524 )
716 #define GPIO_B_PMUX ( *(cc2538_reg_t*)0x400da700 )
717 #define GPIO_B_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400da704 )
718 #define GPIO_B_PI_IEN ( *(cc2538_reg_t*)0x400da710 )
719 #define GPIO_B_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400da718 )
720 #define GPIO_B_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400da71c )
721 #define GPIO_B_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400da720 )
722 #define GPIO_C_DATA ( *(cc2538_reg_t*)0x400db000 )
723 #define GPIO_C_DIR ( *(cc2538_reg_t*)0x400db400 )
724 #define GPIO_C_IS ( *(cc2538_reg_t*)0x400db404 )
725 #define GPIO_C_IBE ( *(cc2538_reg_t*)0x400db408 )
726 #define GPIO_C_IEV ( *(cc2538_reg_t*)0x400db40c )
727 #define GPIO_C_IE ( *(cc2538_reg_t*)0x400db410 )
728 #define GPIO_C_RIS ( *(cc2538_reg_t*)0x400db414 )
729 #define GPIO_C_MIS ( *(cc2538_reg_t*)0x400db418 )
730 #define GPIO_C_IC ( *(cc2538_reg_t*)0x400db41c )
731 #define GPIO_C_AFSEL ( *(cc2538_reg_t*)0x400db420 )
732 #define GPIO_C_GPIOLOCK ( *(cc2538_reg_t*)0x400db520 )
733 #define GPIO_C_GPIOCR ( *(cc2538_reg_t*)0x400db524 )
734 #define GPIO_C_PMUX ( *(cc2538_reg_t*)0x400db700 )
735 #define GPIO_C_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400db704 )
736 #define GPIO_C_PI_IEN ( *(cc2538_reg_t*)0x400db710 )
737 #define GPIO_C_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400db718 )
738 #define GPIO_C_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400db71c )
739 #define GPIO_C_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400db720 )
740 #define GPIO_D_DATA ( *(cc2538_reg_t*)0x400dc000 )
741 #define GPIO_D_DIR ( *(cc2538_reg_t*)0x400dc400 )
742 #define GPIO_D_IS ( *(cc2538_reg_t*)0x400dc404 )
743 #define GPIO_D_IBE ( *(cc2538_reg_t*)0x400dc408 )
744 #define GPIO_D_IEV ( *(cc2538_reg_t*)0x400dc40c )
745 #define GPIO_D_IE ( *(cc2538_reg_t*)0x400dc410 )
746 #define GPIO_D_RIS ( *(cc2538_reg_t*)0x400dc414 )
747 #define GPIO_D_MIS ( *(cc2538_reg_t*)0x400dc418 )
748 #define GPIO_D_IC ( *(cc2538_reg_t*)0x400dc41c )
749 #define GPIO_D_AFSEL ( *(cc2538_reg_t*)0x400dc420 )
750 #define GPIO_D_GPIOLOCK ( *(cc2538_reg_t*)0x400dc520 )
751 #define GPIO_D_GPIOCR ( *(cc2538_reg_t*)0x400dc524 )
752 #define GPIO_D_PMUX ( *(cc2538_reg_t*)0x400dc700 )
753 #define GPIO_D_P_EDGE_CTRL ( *(cc2538_reg_t*)0x400dc704 )
754 #define GPIO_D_PI_IEN ( *(cc2538_reg_t*)0x400dc710 )
755 #define GPIO_D_IRQ_DETECT_ACK ( *(cc2538_reg_t*)0x400dc718 )
756 #define GPIO_D_USB_IRQ_ACK ( *(cc2538_reg_t*)0x400dc71c )
757 #define GPIO_D_IRQ_DETECT_UNMASK ( *(cc2538_reg_t*)0x400dc720 )
758 #define UDMA_STAT ( *(cc2538_reg_t*)0x400ff000 )
759 #define UDMA_CFG ( *(cc2538_reg_t*)0x400ff004 )
760 #define UDMA_CTLBASE ( *(cc2538_reg_t*)0x400ff008 )
761 #define UDMA_ALTBASE ( *(cc2538_reg_t*)0x400ff00c )
762 #define UDMA_WAITSTAT ( *(cc2538_reg_t*)0x400ff010 )
763 #define UDMA_SWREQ ( *(cc2538_reg_t*)0x400ff014 )
764 #define UDMA_USEBURSTSET ( *(cc2538_reg_t*)0x400ff018 )
765 #define UDMA_USEBURSTCLR ( *(cc2538_reg_t*)0x400ff01c )
766 #define UDMA_REQMASKSET ( *(cc2538_reg_t*)0x400ff020 )
767 #define UDMA_REQMASKCLR ( *(cc2538_reg_t*)0x400ff024 )
768 #define UDMA_ENASET ( *(cc2538_reg_t*)0x400ff028 )
769 #define UDMA_ENACLR ( *(cc2538_reg_t*)0x400ff02c )
770 #define UDMA_ALTSET ( *(cc2538_reg_t*)0x400ff030 )
771 #define UDMA_ALTCLR ( *(cc2538_reg_t*)0x400ff034 )
772 #define UDMA_PRIOSET ( *(cc2538_reg_t*)0x400ff038 )
773 #define UDMA_PRIOCLR ( *(cc2538_reg_t*)0x400ff03c )
774 #define UDMA_ERRCLR ( *(cc2538_reg_t*)0x400ff04c )
775 #define UDMA_CHASGN ( *(cc2538_reg_t*)0x400ff500 )
776 #define UDMA_CHIS ( *(cc2538_reg_t*)0x400ff504 )
777 #define UDMA_CHMAP0 ( *(cc2538_reg_t*)0x400ff510 )
778 #define UDMA_CHMAP1 ( *(cc2538_reg_t*)0x400ff514 )
779 #define UDMA_CHMAP2 ( *(cc2538_reg_t*)0x400ff518 )
780 #define UDMA_CHMAP3 ( *(cc2538_reg_t*)0x400ff51c )
781 #define PKA_APTR ( *(cc2538_reg_t*)0x44004000 )
782 #define PKA_BPTR ( *(cc2538_reg_t*)0x44004004 )
783 #define PKA_CPTR ( *(cc2538_reg_t*)0x44004008 )
784 #define PKA_DPTR ( *(cc2538_reg_t*)0x4400400c )
785 #define PKA_ALENGTH ( *(cc2538_reg_t*)0x44004010 )
786 #define PKA_BLENGTH ( *(cc2538_reg_t*)0x44004014 )
787 #define PKA_SHIFT ( *(cc2538_reg_t*)0x44004018 )
788 #define PKA_FUNCTION ( *(cc2538_reg_t*)0x4400401c )
789 #define PKA_COMPARE ( *(cc2538_reg_t*)0x44004020 )
790 #define PKA_MSW ( *(cc2538_reg_t*)0x44004024 )
791 #define PKA_DIVMSW ( *(cc2538_reg_t*)0x44004028 )
792 #define PKA_SEQ_CTRL ( *(cc2538_reg_t*)0x440040c8 )
793 #define PKA_OPTIONS ( *(cc2538_reg_t*)0x440040f4 )
794 #define PKA_SW_REV ( *(cc2538_reg_t*)0x440040f8 )
795 #define PKA_REVISION ( *(cc2538_reg_t*)0x440040fc )
796 #define CCTEST_IO ( *(cc2538_reg_t*)0x44010000 )
797 #define CCTEST_OBSSEL0 ( *(cc2538_reg_t*)0x44010014 )
798 #define CCTEST_OBSSEL1 ( *(cc2538_reg_t*)0x44010018 )
799 #define CCTEST_OBSSEL2 ( *(cc2538_reg_t*)0x4401001c )
800 #define CCTEST_OBSSEL3 ( *(cc2538_reg_t*)0x44010020 )
801 #define CCTEST_OBSSEL4 ( *(cc2538_reg_t*)0x44010024 )
802 #define CCTEST_OBSSEL5 ( *(cc2538_reg_t*)0x44010028 )
803 #define CCTEST_OBSSEL6 ( *(cc2538_reg_t*)0x4401002c )
804 #define CCTEST_OBSSEL7 ( *(cc2538_reg_t*)0x44010030 )
805 #define CCTEST_TR0 ( *(cc2538_reg_t*)0x44010034 )
806 #define CCTEST_USBCTRL ( *(cc2538_reg_t*)0x44010050 )
809 #define XOSC32M_FREQ 32000000
810 #define RCOSC16M_FREQ 16000000
812 #define CC2538_VTOR_ALIGN 512
814 #ifdef __cplusplus
815 }
816 #endif
817 
818 #endif /* _CC2538_ */
819 
SM Timer.
Definition: cc2538.h:83
SSI0.
Definition: cc2538.h:54
11 Cortex-M3 SV Call Interrupt
Definition: cc2538.h:42
uDMA software
Definition: cc2538.h:76
UART1.
Definition: cc2538.h:53
I2C.
Definition: cc2538.h:55
MAC Timer (Alternate)
Definition: cc2538.h:72
void PendSV_Handler(void)
PendSV handler.
Flash memory control.
Definition: cc2538.h:68
SM Timer (Alternate)
Definition: cc2538.h:71
PKA.
Definition: cc2538.h:82
AES.
Definition: cc2538.h:81
enum IRQn IRQn_Type
Interrupt Number Definition.
GPIO port C.
Definition: cc2538.h:50
GPTimer 3B.
Definition: cc2538.h:75
GPIO port B.
Definition: cc2538.h:49
6 Cortex-M3 Usage Fault Interrupt
Definition: cc2538.h:41
ADC.
Definition: cc2538.h:56
void Reset_Handler(void)
Reset handler.
SSI1.
Definition: cc2538.h:73
Analog Comparator.
Definition: cc2538.h:64
15 Cortex-M3 System Tick Interrupt
Definition: cc2538.h:45
System Control.
Definition: cc2538.h:67
void SysTick_Handler(void)
SysTick handler.
GPIO port A.
Definition: cc2538.h:48
void NMI_Handler(void)
NMI handler.
Number of peripheral IDs.
Definition: cc2538.h:86
GPTimer 3A.
Definition: cc2538.h:74
Watchdog Timer.
Definition: cc2538.h:57
MAC Timer.
Definition: cc2538.h:84
14 Cortex-M3 Pend SV Interrupt
Definition: cc2538.h:44
5 Cortex-M3 Bus Fault Interrupt
Definition: cc2538.h:40
4 Cortex-M3 Memory Management Interrupt
Definition: cc2538.h:39
RF TX/RX (Alternate)
Definition: cc2538.h:65
PKA (Alternate)
Definition: cc2538.h:70
void UsageFault_Handler(void)
Usage fault handler.
USB.
Definition: cc2538.h:78
void SVC_Handler(void)
SVC handler.
GPTimer 1B.
Definition: cc2538.h:61
12 Cortex-M3 Debug Monitor Interrupt
Definition: cc2538.h:43
void HardFault_Handler(void)
Hard fault handler.
IRQn
Interrupt Number Definition.
Definition: cc2538.h:33
uDMA error
Definition: cc2538.h:77
void DebugMon_Handler(void)
Debug monitor handler.
GPTimer 2B.
Definition: cc2538.h:63
UART0.
Definition: cc2538.h:52
3 Cortex-M3 Hard Fault Interrupt
Definition: cc2538.h:38
RF Error (Alternate)
Definition: cc2538.h:66
RF Core Error.
Definition: cc2538.h:80
void BusFault_Handler(void)
Bus fault handler.
GPIO port D.
Definition: cc2538.h:51
GPTimer 1A.
Definition: cc2538.h:60
1 Reset Handler
Definition: cc2538.h:36
GPTimer 0B.
Definition: cc2538.h:59
GPTimer 2A.
Definition: cc2538.h:62
AES (Alternate)
Definition: cc2538.h:69
2 Non Maskable Interrupt
Definition: cc2538.h:37
RF Core Rx/Tx.
Definition: cc2538.h:79
void MemManage_Handler(void)
Memory management handler.
GPTimer 0A.
Definition: cc2538.h:58