boards/ek-lm4f120xl/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLK80 1
33 #define CLK50 2
34 #define CLK40 3
35 #define CLK16 4
36 #define CLK1 5
37 #define CLOCK_SOURCE CLK40
38 
44 #define TIMER_NUMOF (2U)
45 #define TIMER_0_EN 1
46 #define TIMER_1_EN 1
47 #define TIMER_IRQ_PRIO 1
48 
49 /* Timer 0 configuration
50  *
51  * WTIMER0 is a 32/64bits timer.
52  * We use timer_a as TIMER_0
53  */
54 #define TIMER_0_CHANNELS 1
55 #define TIMER_0_MAX_VALUE (0xffffffff)
56 #define TIMER_0_ISR isr_wtimer0a
57 #define TIMER_0_IRQ_CHAN Timer0A_IRQn
58 
59 /* Timer 1 configuration
60  *
61  * WTIMER1 is a 32/64bits timer.
62  * We use timer_a as TIMER_1
63  */
64 
65 #define TIMER_1_CHANNELS 1
66 #define TIMER_1_MAX_VALUE (0xffffffff)
67 #define TIMER_1_ISR isr_wtimer1a
68 #define TIMER_1_IRQ_CHAN Timer1A_IRQn
69 
75 #define UART_NUMOF (1U)
76 #define UART_0_EN 1
77 #define UART_1_EN 0
78 #define UART_IRQ_PRIO 1
79 #define UART_CLK ROM_SysCtlClockGet() /* UART clock runs with 40MHz */
80 /* UART 0 device configuration */
81 #define UART_0_DEV UART0_BASE
82 #define UART_0_CLK (40000000)
83 #define UART_0_IRQ_CHAN UART0_IRQn
84 #define UART_0_ISR isr_uart0
85 /* UART 0 pin configuration */
86 #define UART_0_PORT GPIOA
87 #define UART_0_TX_PIN UART_PA1_U0TX
88 #define UART_0_RX_PIN UART_PA0_U0RX
89 
90 /* UART 1 device configuration */
91 #define UART_1_DEV UART1_BASE
92 #define UART_1_CLK (40000000)
93 #define UART_1_IRQ_CHAN UART1_IRQn
94 #define UART_1_ISR isr_uart1
95 
101 #define ADC_NUMOF (12)
102 
108 static const spi_conf_t spi_confs[] = {
109  {
110  .ssi_sysctl = SYSCTL_PERIPH_SSI0,
111  .ssi_base = SSI0_BASE,
112  .gpio_sysctl = SYSCTL_PERIPH_GPIOA,
113  .gpio_port = GPIO_PORTA_BASE,
114  .pins = {
115  .clk = GPIO_PA2_SSI0CLK,
116  .fss = GPIO_PA3_SSI0FSS,
117  .rx = GPIO_PA4_SSI0RX,
118  .tx = GPIO_PA5_SSI0TX,
119  .mask = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5
120  }
121  },
122  {
123  .ssi_sysctl = SYSCTL_PERIPH_SSI1,
124  .ssi_base = SSI1_BASE,
125  .gpio_sysctl = SYSCTL_PERIPH_GPIOF,
126  .gpio_port = GPIO_PORTF_BASE,
127  .pins = {
128  .clk = GPIO_PF2_SSI1CLK,
129  .fss = GPIO_PF3_SSI1FSS,
130  .rx = GPIO_PF0_SSI1RX,
131  .tx = GPIO_PF1_SSI1TX,
132  .mask = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3
133  }
134  },
135  {
136  .ssi_sysctl = SYSCTL_PERIPH_SSI2,
137  .ssi_base = SSI2_BASE,
138  .gpio_sysctl = SYSCTL_PERIPH_GPIOB,
139  .gpio_port = GPIO_PORTB_BASE,
140  .pins = {
141  .clk = GPIO_PB4_SSI2CLK,
142  .fss = GPIO_PB5_SSI2FSS,
143  .rx = GPIO_PB6_SSI2RX,
144  .tx = GPIO_PB7_SSI2TX,
145  .mask = GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7
146  }
147  },
148  {
149  .ssi_sysctl = SYSCTL_PERIPH_SSI3,
150  .ssi_base = SSI3_BASE,
151  .gpio_sysctl = SYSCTL_PERIPH_GPIOD,
152  .gpio_port = GPIO_PORTD_BASE,
153  .pins = {
154  .clk = GPIO_PD0_SSI3CLK,
155  .fss = GPIO_PD1_SSI3FSS,
156  .rx = GPIO_PD2_SSI3RX,
157  .tx = GPIO_PD3_SSI3TX,
158  .mask = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3
159  }
160  },
161 };
162 
163 #define SPI_NUMOF (sizeof(spi_confs) / sizeof(spi_confs[0]))
164 
166 #ifdef __cplusplus
167 }
168 #endif
169 
170 #endif /* PERIPH_CONF_H */
171 
unsigned long ssi_sysctl
SSI device in sysctl.
SPI module configuration options.