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boards/ek-lm4f120xl/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
30 #define CLK80 1
31 #define CLK50 2
32 #define CLK40 3
33 #define CLK16 4
34 #define CLK1 5
35 #define CLOCK_SOURCE CLK40
36 
42 #define TIMER_NUMOF (2U)
43 #define TIMER_0_EN 1
44 #define TIMER_1_EN 1
45 #define TIMER_IRQ_PRIO 1
46 
47 /* Timer 0 configuration
48  *
49  * WTIMER0 is a 32/64bits timer.
50  * We use timer_a as TIMER_0
51  */
52 #define TIMER_0_CHANNELS 1
53 #define TIMER_0_MAX_VALUE (0xffffffff)
54 #define TIMER_0_ISR isr_wtimer0a
55 #define TIMER_0_IRQ_CHAN Timer0A_IRQn
56 
57 /* Timer 1 configuration
58  *
59  * WTIMER1 is a 32/64bits timer.
60  * We use timer_a as TIMER_1
61  */
62 
63 #define TIMER_1_CHANNELS 1
64 #define TIMER_1_MAX_VALUE (0xffffffff)
65 #define TIMER_1_ISR isr_wtimer1a
66 #define TIMER_1_IRQ_CHAN Timer1A_IRQn
67 
73 #define UART_NUMOF (1U)
74 #define UART_0_EN 1
75 #define UART_1_EN 0
76 #define UART_IRQ_PRIO 1
77 #define UART_CLK ROM_SysCtlClockGet() /* UART clock runs with 40MHz */
78 /* UART 0 device configuration */
79 #define UART_0_DEV UART0_BASE
80 #define UART_0_CLK (40000000)
81 #define UART_0_IRQ_CHAN UART0_IRQn
82 #define UART_0_ISR isr_uart0
83 /* UART 0 pin configuration */
84 #define UART_0_PORT GPIOA
85 #define UART_0_TX_PIN UART_PA1_U0TX
86 #define UART_0_RX_PIN UART_PA0_U0RX
87 
88 /* UART 1 device configuration */
89 #define UART_1_DEV UART1_BASE
90 #define UART_1_CLK (40000000)
91 #define UART_1_IRQ_CHAN UART1_IRQn
92 #define UART_1_ISR isr_uart1
93 
99 #define ADC_NUMOF (12)
100 
102 #ifdef __cplusplus
103 }
104 #endif
105 
106 #endif /* PERIPH_CONF_H */
107