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periph_cpu.h
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1/*
2 * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
3 * Copyright (C) 2017 Marc Poulhiès <dkm@kataplop.net>
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CPU_H
22#define PERIPH_CPU_H
23
24#include "cpu.h"
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
34#define HAVE_GPIO_T
35typedef uint32_t gpio_t;
36#define GPIO_PIN(x, y) ((gpio_t)((x<<4) | y))
39#ifndef DOXYGEN
44#define HAVE_GPIO_MODE_T
45typedef enum {
46 GPIO_IN = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD << 4)),
47 GPIO_IN_PD = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPD << 4)),
48 GPIO_IN_PU = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPU << 4)),
49 GPIO_OUT = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_STD << 4)),
50 GPIO_OD = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD << 4)),
51 GPIO_OD_PU = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD_WPU << 4)),
54#endif /* ndef DOXYGEN */
55
60#define HAVE_GPIO_DIR_T
61typedef enum {
62 GPIO_DIR_IN = GPIO_DIR_MODE_IN,
63 GPIO_DIR_OUT = GPIO_DIR_MODE_OUT
67#ifndef DOXYGEN
72#define HAVE_GPIO_FLANK_T
73typedef enum {
74 GPIO_FALLING = GPIO_FALLING_EDGE,
75 GPIO_RISING = GPIO_RISING_EDGE,
76 GPIO_BOTH = GPIO_BOTH_EDGES
79#endif /* ndef DOXYGEN */
80
84enum {
85 PORT_A = 0,
86 PORT_B = 1,
87 PORT_C = 2,
88 PORT_D = 3,
89 PORT_E = 4,
90 PORT_F = 5,
91};
92
96#ifndef DOXYGEN
97#define HAVE_ADC_RES_T
98typedef enum {
99 ADC_RES_6BIT = 0xa00,
100 ADC_RES_8BIT = 0xb00,
101 ADC_RES_10BIT = ADC_RES_10BIT_S,
102 ADC_RES_12BIT = ADC_RES_12BIT_S,
103 ADC_RES_14BIT = 0xc00,
104 ADC_RES_16BIT = 0xd00,
105} adc_res_t;
106#endif /* ndef DOXYGEN */
107
111typedef struct {
112 uint32_t dev;
113 uint32_t max;
114 int irqn;
115 uint32_t sysctl;
116 uint32_t intbase;
119
125#define SPI_HWCS(x) (UINT_MAX - 1)
126
131typedef struct {
132 unsigned long ssi_sysctl;
133 unsigned long ssi_base;
134 unsigned long gpio_sysctl;
135 unsigned long gpio_port;
136 struct {
137 unsigned long clk;
138 unsigned long fss;
139 unsigned long rx;
140 unsigned long tx;
141 unsigned long mask;
142 } pins;
143} spi_conf_t;
150#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
151#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
152#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
153#define PERIPH_SPI_NEEDS_INIT_CS 1
156#ifndef DOXYGEN
161#define HAVE_SPI_CLK_T 1
162typedef enum {
163 SPI_CLK_100KHZ = 100000,
164 SPI_CLK_400KHZ = 400000,
165 SPI_CLK_1MHZ = 1000000,
166 SPI_CLK_4MHZ = 4000000,
167 SPI_CLK_5MHZ = 5000000,
168 SPI_CLK_10MHZ = 10000000,
169} spi_clk_t;
176#define HAVE_SPI_MODE_T 1
177typedef enum {
178 SPI_MODE_0 = SSI_FRF_MOTO_MODE_0,
179 SPI_MODE_1 = SSI_FRF_MOTO_MODE_1,
180 SPI_MODE_2 = SSI_FRF_MOTO_MODE_2,
181 SPI_MODE_3 = SSI_FRF_MOTO_MODE_0,
182} spi_mode_t;
184#endif /* ndef DOXYGEN */
185
186#ifdef __cplusplus
187}
188#endif
189
190#endif /* PERIPH_CPU_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_F
port F
Definition periph_cpu.h:52
@ PORT_E
port E
Definition periph_cpu.h:51
@ PORT_A
port A
Definition periph_cpu.h:47
@ PORT_D
port D
Definition periph_cpu.h:50
gpio_flank_t
Definition periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
adc_res_t
Possible ADC resolution settings.
Definition adc.h:93
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:99
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:97
gpio_dir_t
Definition periph_cpu.h:61
@ GPIO_DIR_IN
configure pin as input
Definition periph_cpu.h:62
@ GPIO_DIR_OUT
configure pin as output
Definition periph_cpu.h:63
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
SPI device configuration.
Definition periph_cpu.h:337
unsigned long fss
pin used for FSS
Definition periph_cpu.h:138
unsigned long tx
pin used for MOSI
Definition periph_cpu.h:140
unsigned long clk
pin used for SCK
Definition periph_cpu.h:137
unsigned long mask
Pin mask.
Definition periph_cpu.h:141
unsigned long gpio_sysctl
GPIO device in sysctl.
Definition periph_cpu.h:134
unsigned long rx
pin used for MISO
Definition periph_cpu.h:139
unsigned long ssi_base
SSI base address.
Definition periph_cpu.h:133
unsigned long gpio_port
GPIO port.
Definition periph_cpu.h:135
unsigned long ssi_sysctl
SSI device in sysctl.
Definition periph_cpu.h:132
Timer device configuration.
Definition periph_cpu.h:264
uint32_t sysctl
Address of timer system control.
Definition periph_cpu.h:115
int irqn
Number of the higher timer IRQ channel.
Definition periph_cpu.h:114
int channels
Number of channels for the timer.
Definition periph_cpu.h:117
uint32_t intbase
Interrupt base of timer.
Definition periph_cpu.h:116
uint32_t dev
Address of timer base.
Definition periph_cpu.h:112