periph_cpu.h

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/*
 * SPDX-FileCopyrightText: 2021 Freie Universität Berlin
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifndef DOXYGEN

#define ADC_T_ADCVREG_STUP_US (20)

#define ADC_DEVS            (1U)

#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = (ADC_CFGR1_RES),    
    ADC_RES_8BIT  = (ADC_CFGR1_RES_1),  
    ADC_RES_10BIT = (ADC_CFGR1_RES_0),  
    ADC_RES_12BIT = (0x00),             
    ADC_RES_14BIT = (0xfe), 
    ADC_RES_16BIT = (0xff)  
} adc_res_t;

#define STM32_BOOTLOADER_ADDR   (0x1FFF0000)

#define VBAT_ADC_RES        ADC_RES_12BIT
#define VBAT_ADC_MAX        4095
 
#endif /* ndef DOXYGEN */

#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT     GPIO_PIN(PORT_A, 7)
#define CPU_STM32WL_SUBGHZSPI_DEBUG_MOSIOUT_AF  GPIO_AF13
 
#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT     GPIO_PIN(PORT_A, 6)
#define CPU_STM32WL_SUBGHZSPI_DEBUG_MISOOUT_AF  GPIO_AF13
 
#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT      GPIO_PIN(PORT_A, 5)
#define CPU_STM32WL_SUBGHZSPI_DEBUG_SCKOUT_AF   GPIO_AF13
 
#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT      GPIO_PIN(PORT_A, 4)
#define CPU_STM32WL_SUBGHZSPI_DEBUG_NSSOUT_AF   GPIO_AF13

#define CPU_STM32WL_SUBGHZ_RF_BUSY              GPIO_PIN(PORT_A, 12)
#define CPU_STM32WL_SUBGHZ_RF_BUSY_AF           GPIO_AF6

#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET      GPIO_PIN(PORT_A, 11)
#define CPU_STM32WL_SUBGHZ_DEBUG_RF_NRESET_AF   GPIO_AF13

#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY     GPIO_PIN(PORT_B, 2)
#define CPU_STM32WL_SUBGHZ_DEBUG_RF_SMPSRDY_AF  GPIO_AF13

#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY      GPIO_PIN(PORT_B, 4)
#define CPU_STM32WL_SUBGHZ_DEBUG_RF_LDORDY_AF   GPIO_AF13

#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY    GPIO_PIN(PORT_A, 10)
#define CPU_STM32WL_SUBGHZ_DEBUG_RF_HSE32RDY_AF GPIO_AF13

#ifdef DOXYGEN
#define CONFIG_STM32_WLX5XX_SUBGHZ_DEBUG
#endif
 
#ifdef __cplusplus
}
#endif