periph_cpu.h

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/*
 * Copyright (C) 2015-2016 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_F1_PERIPH_CPU_H
#define PERIPH_F1_PERIPH_CPU_H
 
#include "cpu_conf.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifndef DOXYGEN
 
#if defined(CPU_LINE_STM32F103xB) || defined(CPU_LINE_STM32F103xE)
#define STM32_BOOTLOADER_ADDR   (0x1FFFF000)
#endif
 
#define STM32_OPTION_BYTES   ((uint32_t*) 0x1FFFF800)
#define GET_RDP(x) (x & 0xFF)
 
#endif /* ndef DOXYGEN */
 
#define RTT_IRQ_PRIO        1
 
#define RTT_DEV             RTC
#define RTT_IRQ             RTC_IRQn
#define RTT_ISR             isr_rtc
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                  /* in Hz */
#define RTT_MIN_FREQUENCY   (1U)                      /* in Hz */
/* RTC frequency of 32kHz is not recommended, see RM0008 Rev 20, p490 */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY / 2) /* in Hz */
#define ADC_DEVS            (2U)
 
enum {
    GPIO_CRL_MODE0_INPUT            = (0x0 << GPIO_CRL_MODE0_Pos),
    GPIO_CRL_MODE0_OUTPUT_10MHZ     = (0x1 << GPIO_CRL_MODE0_Pos),
    GPIO_CRL_MODE0_OUTPUT_2MHZ      = (0x2 << GPIO_CRL_MODE0_Pos),
    GPIO_CRL_MODE0_OUTPUT_50MHZ     = (0x3 << GPIO_CRL_MODE0_Pos),
};
 
enum {
    GPIO_CRL_CNF0_INPUT_ANALOG      = (0x0 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_INPUT_FLOATING    = (0x1 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_INPUT_PULL        = (0x2 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_OUTPUT_PUSH_PULL  = (0x0 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_OUTPUT_OPEN_DRAIN = (0x1 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_AF_PUSH_PULL      = (0x2 << GPIO_CRL_CNF0_Pos),
    GPIO_CRL_CNF0_AF_OPEN_DRAIN     = (0x3 << GPIO_CRL_CNF0_Pos),
};
typedef enum {
    SWJ_CFG_FULL_SWJ    = 0,
    SWJ_CFG_NO_NJTRST   = AFIO_MAPR_SWJ_CFG_NOJNTRST,
    SWJ_CFG_NO_JTAG_DP  = AFIO_MAPR_SWJ_CFG_JTAGDISABLE,
    SWJ_CFG_DISABLED    = AFIO_MAPR_SWJ_CFG_DISABLE,
} afio_mapr_swj_cfg_t;
 
#ifndef CONFIG_AFIO_MAPR_SWJ_CFG
#define CONFIG_AFIO_MAPR_SWJ_CFG    SWJ_CFG_NO_JTAG_DP
#endif
 
static inline uint32_t afio_mapr_read(void)
{
    return AFIO->MAPR & (~(AFIO_MAPR_SWJ_CFG_Msk));
}
 
static inline void afio_mapr_write(uint32_t new_value)
{
    AFIO->MAPR = CONFIG_AFIO_MAPR_SWJ_CFG | new_value;
}
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_F1_PERIPH_CPU_H */