33#define STM32_BOOTLOADER_ADDR 
   41#define CPUID_LEN           (12U) 
   47#define CPUID_ADDR          (UID_BASE) 
   53#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \ 
   54    defined(CPU_FAM_STM32F3) 
   55#define CLOCK_LSI           (40000U) 
   56#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) 
   57#define CLOCK_LSI           (37000U) 
   58#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ 
   59      defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \ 
   60      defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \ 
   61      defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ 
   62      defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \ 
   63      defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0) 
   64#define CLOCK_LSI           (32000U) 
   66#error "error: LSI clock speed not defined for your target CPU" 
   70#if     defined(CPU_FAM_STM32G4) || \ 
   71        defined(CPU_FAM_STM32L4) || \ 
   72        defined(CPU_FAM_STM32L5) || \ 
   73        defined(CPU_FAM_STM32U5) || \ 
   74        defined(CPU_FAM_STM32WB) || \ 
   75        defined(CPU_FAM_STM32WL) 
   76            #define APB1_PERIPH_EN              RCC->APB1ENR1 
   77            #define APB12_PERIPH_EN             RCC->APB1ENR2 
   78#elif   defined(CPU_FAM_STM32C0) || \ 
   79        defined(CPU_FAM_STM32G0) 
   80            #define APB1_PERIPH_EN              RCC->APBENR1 
   81            #define APB12_PERIPH_EN             RCC->APBENR2 
   82#elif   defined(CPU_FAM_STM32MP1) 
   83            #define APB1_PERIPH_EN              RCC->MC_APB1ENSETR 
   84            #define APB1_PERIPH_DIS             RCC->MC_APB1ENCLRR 
   85#elif   defined(APB1PERIPH_BASE) || \ 
   86        defined(CPU_FAM_STM32F0) || \ 
   87        defined(CPU_FAM_STM32L0) 
   88            #define APB1_PERIPH_EN              RCC->APB1ENR 
   92#if     defined(CPU_FAM_STM32MP1) 
   93            #define APB2_PERIPH_EN              RCC->MC_APB2ENSETR 
   94            #define APB2_PERIPH_DIS             RCC->MC_APB2ENCLRR 
   95#elif   defined(APB2PERIPH_BASE) || \ 
   96        defined(CPU_FAM_STM32F0) || \ 
   97        defined(CPU_FAM_STM32L0) 
   98            #define APB2_PERIPH_EN              RCC->APB2ENR 
  102#if     defined(CPU_FAM_STM32WB) 
  104            #undef APB3_PERIPH_EN                
  105#elif   defined(APB3PERIPH_BASE) || \ 
  106        defined(APB3PERIPH_BASE_S) 
  107            #define APB3_PERIPH_EN              RCC->APB3ENR 
  111#if     defined(AHBPERIPH_BASE) || \ 
  112        defined(CPU_FAM_STM32F3) 
  113            #define AHB_PERIPH_EN               RCC->AHBENR 
  114#elif   defined(CPU_FAM_STM32MP1) 
  116            #undef AHB1_PERIPH_EN                
  117            #undef AHB1_PERIPH_DIS               
  118#elif   defined(AHB1PERIPH_BASE) 
  119            #define AHB1_PERIPH_EN              RCC->AHB1ENR 
  123#if     defined(CPU_FAM_STM32F0) || \ 
  124        defined(CPU_FAM_STM32F3) 
  126            #undef AHB2_PERIPH_EN                
  127#elif   defined(CPU_FAM_STM32U5) 
  128            #define AHB2_PERIPH_EN              RCC->AHB2ENR1 
  129            #define AHB22_PERIPH_EN             RCC->AHB2ENR2 
  130#elif   defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT) 
  131            #define AHB2_PERIPH_EN              RCC->AHB2ENR 
  132#elif   defined(CPU_FAM_STM32MP1) 
  133            #define AHB2_PERIPH_EN              RCC->MC_AHB2ENSETR 
  134            #define AHB2_PERIPH_DIS             RCC->MC_AHB2ENCLRR 
  135#elif   defined(AHB2PERIPH_BASE) 
  136            #define AHB2_PERIPH_EN              RCC->AHB2ENR 
  140#if     defined(CPU_FAM_STM32F3) 
  142            #undef AHB3_PERIPH_EN                
  143#elif   defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT) 
  144            #define AHB3_PERIPH_EN              RCC->AHB3ENR 
  145#elif   defined(CPU_FAM_STM32MP1) 
  146            #define AHB3_PERIPH_EN              RCC->MC_AHB3ENSETR 
  147            #define AHB3_PERIPH_DIS             RCC->MC_AHB3ENCLRR 
  148#elif   defined(AHB3PERIPH_BASE) || \ 
  149        defined(AHB3PERIPH_BASE_S) || \ 
  150        defined(CPU_FAM_STM32F2) || \ 
  151        defined(CPU_FAM_STM32F7) || \ 
  152        defined(CPU_FAM_STM32G4) || \ 
  153        defined(CPU_FAM_STM32L4) 
  154            #define AHB3_PERIPH_EN              RCC->AHB3ENR 
  158#if     defined(CPU_FAM_STM32MP1) 
  159            #define AHB4_PERIPH_EN              RCC->MC_AHB4ENSETR 
  160            #define AHB4_PERIPH_DIS             RCC->MC_AHB4ENCLRR 
  161#elif   defined(AHB4PERIPH_BASE) 
  163            #define AHB4_PERIPH_EN              RCC->AHB3ENR 
  167#if     defined(IOPPERIPH_BASE) || \ 
  168        defined(RCC_IOPENR_GPIOAEN) || \ 
  169        defined(RCC_IOPENR_IOPAEN) 
  170            #define IOP_PERIPH_EN               RCC->IOPENR 
  177#if defined(APB1_PERIPH_EN) 
  180#if defined(APB12_PERIPH_EN) 
  183#if defined(APB2_PERIPH_EN) 
  186#if defined(APB3_PERIPH_EN) 
  189#if defined(AHB_PERIPH_EN) 
  192#if defined(AHB1_PERIPH_EN) 
  195#if defined(AHB2_PERIPH_EN) 
  198#if defined(AHB22_PERIPH_EN) 
  201#if defined(AHB3_PERIPH_EN) 
  204#if defined(AHB4_PERIPH_EN) 
  207#if defined(IOP_PERIPH_EN) 
 
@ APB1
Advanced Peripheral Bus 1.
@ AHB
Advanced High-performance Bus.
@ APB2
Advanced Peripheral Bus 2.
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
@ BUS_NUMOF
number of buses