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cpu_common.h
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1/*
2 * SPDX-FileCopyrightText: 2016 Freie Universität Berlin
3 * SPDX-FileCopyrightText: 2017 OTA keys S.A.
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
19
20#include <stdint.h>
21
22#include "cpu_conf.h"
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#ifdef Doxygen
33#define STM32_BOOTLOADER_ADDR
34#endif
35
41#define CPUID_LEN (12U)
42
46#ifndef CPUID_ADDR
47#define CPUID_ADDR (UID_BASE)
48#endif
49
53#if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
54 defined(CPU_FAM_STM32F3)
55#define CLOCK_LSI (40000U)
56#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
57#define CLOCK_LSI (37000U)
58#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
59 defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
60 defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
61 defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
62 defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) || \
63 defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
64#define CLOCK_LSI (32000U)
65#else
66#error "error: LSI clock speed not defined for your target CPU"
67#endif
68
69/* if CPU has APB1 bus */
70#if defined(CPU_FAM_STM32G4) || \
71 defined(CPU_FAM_STM32L4) || \
72 defined(CPU_FAM_STM32L5) || \
73 defined(CPU_FAM_STM32U5) || \
74 defined(CPU_FAM_STM32WB) || \
75 defined(CPU_FAM_STM32WL)
76 #define APB1_PERIPH_EN RCC->APB1ENR1
77 #define APB12_PERIPH_EN RCC->APB1ENR2
78#elif defined(CPU_FAM_STM32C0) || \
79 defined(CPU_FAM_STM32G0)
80 #define APB1_PERIPH_EN RCC->APBENR1
81 #define APB12_PERIPH_EN RCC->APBENR2
82#elif defined(CPU_FAM_STM32MP1)
83 #define APB1_PERIPH_EN RCC->MC_APB1ENSETR
84 #define APB1_PERIPH_DIS RCC->MC_APB1ENCLRR
85#elif defined(APB1PERIPH_BASE) || \
86 defined(CPU_FAM_STM32F0) || \
87 defined(CPU_FAM_STM32L0)
88 #define APB1_PERIPH_EN RCC->APB1ENR
89#endif
90
91/* if CPU has APB2 bus */
92#if defined(CPU_FAM_STM32MP1)
93 #define APB2_PERIPH_EN RCC->MC_APB2ENSETR
94 #define APB2_PERIPH_DIS RCC->MC_APB2ENCLRR
95#elif defined(APB2PERIPH_BASE) || \
96 defined(CPU_FAM_STM32F0) || \
97 defined(CPU_FAM_STM32L0)
98 #define APB2_PERIPH_EN RCC->APB2ENR
99#endif
100
101/* if CPU has APB3 bus */
102#if defined(CPU_FAM_STM32WB)
103 /* CPU has APB3, but no periph enable registers for the bus. */
104 #undef APB3_PERIPH_EN /* not defined */
105#elif defined(APB3PERIPH_BASE) || \
106 defined(APB3PERIPH_BASE_S)
107 #define APB3_PERIPH_EN RCC->APB3ENR
108#endif
109
110/* if CPU has AHB/AHB1 bus */
111#if defined(AHBPERIPH_BASE) || \
112 defined(CPU_FAM_STM32F3)
113 #define AHB_PERIPH_EN RCC->AHBENR
114#elif defined(CPU_FAM_STM32MP1)
115 /* CPU has AHB1, but no periph enable registers for the bus. */
116 #undef AHB1_PERIPH_EN /* not defined */
117 #undef AHB1_PERIPH_DIS /* not defined */
118#elif defined(AHB1PERIPH_BASE)
119 #define AHB1_PERIPH_EN RCC->AHB1ENR
120#endif
121
122/* if CPU has AHB2 bus */
123#if defined(CPU_FAM_STM32F0) || \
124 defined(CPU_FAM_STM32F3)
125 /* CPU has AHB2, but no periph enable registers for the bus. */
126 #undef AHB2_PERIPH_EN /* not defined */
127#elif defined(CPU_FAM_STM32U5)
128 #define AHB2_PERIPH_EN RCC->AHB2ENR1
129 #define AHB22_PERIPH_EN RCC->AHB2ENR2
130#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)
131 #define AHB2_PERIPH_EN RCC->AHB2ENR
132#elif defined(CPU_FAM_STM32MP1)
133 #define AHB2_PERIPH_EN RCC->MC_AHB2ENSETR
134 #define AHB2_PERIPH_DIS RCC->MC_AHB2ENCLRR
135#elif defined(AHB2PERIPH_BASE)
136 #define AHB2_PERIPH_EN RCC->AHB2ENR
137#endif
138
139/* if CPU has AHB3 bus */
140#if defined(CPU_FAM_STM32F3)
141 /* CPU has AHB3, but no periph enable registers for the bus. */
142 #undef AHB3_PERIPH_EN /* not defined */
143#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB3_SUPPORT)
144 #define AHB3_PERIPH_EN RCC->AHB3ENR
145#elif defined(CPU_FAM_STM32MP1)
146 #define AHB3_PERIPH_EN RCC->MC_AHB3ENSETR
147 #define AHB3_PERIPH_DIS RCC->MC_AHB3ENCLRR
148#elif defined(AHB3PERIPH_BASE) || \
149 defined(AHB3PERIPH_BASE_S) || \
150 defined(CPU_FAM_STM32F2) || \
151 defined(CPU_FAM_STM32F7) || \
152 defined(CPU_FAM_STM32G4) || \
153 defined(CPU_FAM_STM32L4)
154 #define AHB3_PERIPH_EN RCC->AHB3ENR
155#endif
156
157/* if CPU has AHB4 bus */
158#if defined(CPU_FAM_STM32MP1)
159 #define AHB4_PERIPH_EN RCC->MC_AHB4ENSETR
160 #define AHB4_PERIPH_DIS RCC->MC_AHB4ENCLRR
161#elif defined(AHB4PERIPH_BASE)
162 /* AHB3ENR is not a typo here. It controls both AHB3 and AHB4. */
163 #define AHB4_PERIPH_EN RCC->AHB3ENR
164#endif
165
166/* if CPU has IOP bus */
167#if defined(IOPPERIPH_BASE) || \
168 defined(RCC_IOPENR_GPIOAEN) || \
169 defined(RCC_IOPENR_IOPAEN)
170 #define IOP_PERIPH_EN RCC->IOPENR
171#endif
172
176typedef enum {
177#if defined(APB1_PERIPH_EN)
178 APB1,
179#endif
180#if defined(APB12_PERIPH_EN)
181 APB12,
182#endif
183#if defined(APB2_PERIPH_EN)
184 APB2,
185#endif
186#if defined(APB3_PERIPH_EN)
187 APB3,
188#endif
189#if defined(AHB_PERIPH_EN)
190 AHB,
191#endif
192#if defined(AHB1_PERIPH_EN)
193 AHB1,
194#endif
195#if defined(AHB2_PERIPH_EN)
196 AHB2,
197#endif
198#if defined(AHB22_PERIPH_EN)
199 AHB22,
200#endif
201#if defined(AHB3_PERIPH_EN)
202 AHB3,
203#endif
204#if defined(AHB4_PERIPH_EN)
205 AHB4,
206#endif
207#if defined(IOP_PERIPH_EN)
208 IOP,
209#endif
210 BUS_NUMOF
211} bus_t;
212
220uint32_t periph_apb_clk(bus_t bus);
221
229uint32_t periph_timer_clk(bus_t bus);
230
237void periph_clk_en(bus_t bus, uint32_t mask);
238
245void periph_clk_dis(bus_t bus, uint32_t mask);
246
253void periph_lpclk_en(bus_t bus, uint32_t mask);
254
261void periph_lpclk_dis(bus_t bus, uint32_t mask);
262
263#ifdef __cplusplus
264}
265#endif
266
bus_t
bus_t
On-Chip buses.
Definition periph_cpu.h:73
APB1
@ APB1
Advanced Peripheral Bus 1.
Definition periph_cpu.h:75
AHB
@ AHB
Advanced High-performance Bus.
Definition periph_cpu.h:74
APB2
@ APB2
Advanced Peripheral Bus 2.
Definition periph_cpu.h:76
periph_apb_clk
uint32_t periph_apb_clk(bus_t bus)
Get the actual bus clock frequency for the APB buses.
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
periph_timer_clk
uint32_t periph_timer_clk(bus_t bus)
Get the actual timer clock frequency.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
BUS_NUMOF
@ BUS_NUMOF
number of buses
Definition cpu_common.h:210