cfg_timer_default.h File Reference

Default timer configuration for SODAQ boards. More...

Detailed Description

Default timer configuration for SODAQ boards.

Author
Kees Bakker kees@.nosp@m.soda.nosp@m.q.com

Definition in file cfg_timer_default.h.

#include <stdint.h>
#include "cpu.h"
#include "periph_cpu.h"
+ Include dependency graph for cfg_timer_default.h:

Go to the source code of this file.

Timer peripheral configuration

#define TIMER_0_MAX_VALUE   0xffff
 
#define TIMER_0_ISR   isr_tc3
 
#define TIMER_1_ISR   isr_tc4
 
#define TIMER_NUMOF   ARRAY_SIZE(timer_config)
 
static const tc32_conf_t timer_config []
 

Macro Definition Documentation

◆ TIMER_0_ISR

#define TIMER_0_ISR   isr_tc3

Definition at line 65 of file cfg_timer_default.h.

◆ TIMER_0_MAX_VALUE

#define TIMER_0_MAX_VALUE   0xffff

Definition at line 62 of file cfg_timer_default.h.

◆ TIMER_1_ISR

#define TIMER_1_ISR   isr_tc4

Definition at line 66 of file cfg_timer_default.h.

◆ TIMER_NUMOF

#define TIMER_NUMOF   ARRAY_SIZE(timer_config)

Definition at line 68 of file cfg_timer_default.h.

Variable Documentation

◆ timer_config

const tc32_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
.gclk_src = SAM0_GCLK_MAIN,
.flags = TC_CTRLA_MODE_COUNT16,
},
{
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
.gclk_src = SAM0_GCLK_MAIN,
.flags = TC_CTRLA_MODE_COUNT32,
}
}
#define SAM0_GCLK_MAIN
120 MHz main clock
Definition: periph_cpu.h:73

Definition at line 35 of file cfg_timer_default.h.