periph_cpu.h

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/*
 * Copyright (C) 2015-2016 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include "periph_cpu_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CPU_BACKUP_RAM_NOT_RETAINED (1)
 
#define PM_NUM_MODES           (3)
#define SAML21_PM_MODE_BACKUP  (0)  
#define SAML21_PM_MODE_STANDBY (1)  
#define SAML21_PM_MODE_IDLE    (2)  
#define SAM0_GPIO_PM_BLOCK        SAML21_PM_MODE_BACKUP   
#define SAM0_RTCRTT_PM_BLOCK      SAML21_PM_MODE_BACKUP   
#define SAM0_SPI_PM_BLOCK         SAML21_PM_MODE_STANDBY  
#define SAM0_TIMER_PM_BLOCK       SAML21_PM_MODE_STANDBY  
#define SAM0_UART_PM_BLOCK        SAML21_PM_MODE_STANDBY  
#define SAM0_USB_IDLE_PM_BLOCK    SAML21_PM_MODE_BACKUP   
#define SAM0_USB_ACTIVE_PM_BLOCK  SAML21_PM_MODE_STANDBY  
#ifndef PM_BLOCKER_INITIAL
#define PM_BLOCKER_INITIAL      { 0, 0, 0 }
#endif
 
enum {
    SAM0_GCLK_MAIN  = 0,                 
    SAM0_GCLK_TIMER = 1,                 
    SAM0_GCLK_32KHZ = 2,                 
    SAM0_GCLK_48MHZ = 3,                 
};
static const gpio_t sam0_adc_pins[1][20] = {
    {
        GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8),  GPIO_PIN(PB, 9),
        GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6),  GPIO_PIN(PA, 7),
        GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2),  GPIO_PIN(PB, 3),
        GPIO_PIN(PB, 4), GPIO_PIN(PB, 5), GPIO_PIN(PB, 6),  GPIO_PIN(PB, 7),
        GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
    }
};
 
#define ADC_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN7 
#define ADC_INPUTCTRL_MUXPOS_PB00 ADC_INPUTCTRL_MUXPOS_AIN8 
#define ADC_INPUTCTRL_MUXPOS_PB01 ADC_INPUTCTRL_MUXPOS_AIN9 
#define ADC_INPUTCTRL_MUXPOS_PB02 ADC_INPUTCTRL_MUXPOS_AIN10 
#define ADC_INPUTCTRL_MUXPOS_PB03 ADC_INPUTCTRL_MUXPOS_AIN11 
#define ADC_INPUTCTRL_MUXPOS_PB04 ADC_INPUTCTRL_MUXPOS_AIN12 
#define ADC_INPUTCTRL_MUXPOS_PB05 ADC_INPUTCTRL_MUXPOS_AIN13 
#define ADC_INPUTCTRL_MUXPOS_PB06 ADC_INPUTCTRL_MUXPOS_AIN14 
#define ADC_INPUTCTRL_MUXPOS_PB07 ADC_INPUTCTRL_MUXPOS_AIN15 
#define ADC_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN16 
#define ADC_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN17 
#define ADC_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN18 
#define ADC_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN19 
#define ADC_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0 
#define ADC_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1 
#define ADC_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN2 
#define ADC_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN3 
#define ADC_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN4 
#define ADC_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN5 
#define ADC_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN6 
#define ADC_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN7 
#define DAC_RES_BITS        (12)
 
#define DAC_NUMOF           (2)
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                      /* in Hz */
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 512U)  /* in Hz */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY)         /* in Hz */
/* determined by tests/sys/ztimer_underflow */
#define RTT_MIN_OFFSET      (8U)
struct sam0_aux_cfg_mapping {
    uint64_t bootloader_size            :  3; 
    uint64_t reserved_0                 :  1; 
    uint64_t eeprom_size                :  3; 
    uint64_t reserved_1                 :  1; 
    uint64_t bod33_level                :  6; 
    uint64_t bod33_enable               :  1; 
    uint64_t bod33_action               :  2; 
    uint64_t reserved_2                 :  9; 
    uint64_t wdt_enable                 :  1; 
    uint64_t wdt_always_on              :  1; 
    uint64_t wdt_period                 :  4; 
    uint64_t wdt_window                 :  4; 
    uint64_t wdt_ewoffset               :  4; 
    uint64_t wdt_window_enable          :  1; 
    uint64_t bod33_hysteresis           :  1; 
    uint64_t reserved_3                 :  6; 
    uint64_t nvm_locks                  : 16; 
};
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */