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board.h
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1/*
2 * Copyright (C) 2018 Eistec AB
3 * Copyright (C) 2018 HAW Hamburg
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser General
6 * Public License v2.1. See the file LICENSE in the top level directory for more
7 * details.
8 */
9
21#ifndef BOARD_H
22#define BOARD_H
23
24#include "cpu.h"
25#include "periph_conf.h"
26
27#ifdef __cplusplus
28extern "C"
29{
30#endif
31
32/* Set the FOPT bit to disable NMI so that we can use it as a GPIO pin for
33 * the LED (PTB18) */
34#define KINETIS_FOPT (0xff & ~(NV_FOPT_NMI_DIS_MASK))
35
40#define LED0_PIN GPIO_PIN(PORT_B, 3)
41#define LED0_MASK (1 << 3)
42#define LED0_ON (GPIOB->PCOR = LED0_MASK)
43#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
44#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
45
46#define LED1_PIN GPIO_PIN(PORT_B, 1)
47#define LED1_MASK (1 << 1)
48#define LED1_ON (GPIOB->PCOR = LED1_MASK)
49#define LED1_OFF (GPIOB->PSOR = LED1_MASK)
50#define LED1_TOGGLE (GPIOB->PTOR = LED1_MASK)
51
52#define LED2_PIN GPIO_PIN(PORT_B, 0)
53#define LED2_MASK (1 << 0)
54#define LED2_ON (GPIOB->PCOR = LED2_MASK)
55#define LED2_OFF (GPIOB->PSOR = LED2_MASK)
56#define LED2_TOGGLE (GPIOB->PTOR = LED2_MASK)
57
58#define LED3_PIN GPIO_PIN(PORT_B, 18)
59#define LED3_MASK (1 << 18)
60#define LED3_ON (GPIOB->PCOR = LED3_MASK)
61#define LED3_OFF (GPIOB->PSOR = LED3_MASK)
62#define LED3_TOGGLE (GPIOB->PTOR = LED3_MASK)
69/* Pressing SW1 will short this pin to ground but there are no external pull
70 * resistors, use internal pull-up on the pin */
71/* BTN0 is mapped to SW1 */
72#define BTN0_PIN GPIO_PIN(PORT_C, 5)
73#define BTN0_MODE GPIO_IN_PU
80#define V_PERIPH_PIN GPIO_PIN(PORT_C, 19)
81#define V_PERIPH_MASK (1 << 19)
82#define V_PERIPH_ON (GPIOC->PSOR = V_PERIPH_MASK)
83#define V_PERIPH_OFF (GPIOC->PCOR = V_PERIPH_MASK)
90#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
91/* PIT xtimer configuration */
92#define XTIMER_DEV (TIMER_PIT_DEV(0))
93#define XTIMER_CHAN (0)
94/* Default xtimer settings should work on the PIT */
95#else
96/* LPTMR xtimer configuration */
97#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
98#define XTIMER_CHAN (0)
99/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
100#define XTIMER_WIDTH (16)
101#define XTIMER_BACKOFF (5)
102#define XTIMER_ISR_BACKOFF (5)
103#define XTIMER_HZ (32768ul)
104#endif
111#define CONFIG_ZTIMER_USEC_TYPE ZTIMER_TYPE_PERIPH_TIMER
112#define CONFIG_ZTIMER_USEC_DEV (TIMER_PIT_DEV(0))
119#define CCS811_PARAM_I2C_DEV (I2C_DEV(0))
120#define CCS811_PARAM_I2C_ADDR (0x5A)
121#define CCS811_PARAM_RESET_PIN (GPIO_UNDEF)
122#define CCS811_PARAM_WAKE_PIN (GPIO_PIN(1, 2))
123#define CCS811_PARAM_INT_PIN (GPIO_PIN(1, 3))
124#define CCS811_PARAM_INT_MODE (CCS811_INT_NONE)
131#define TCS37727_PARAM_I2C (I2C_DEV(0))
132#define TCS37727_PARAM_ADDR (0x29)
139#define MMA8X5X_PARAM_I2C (I2C_DEV(0))
140#define MMA8X5X_PARAM_ADDR (0x1D)
143#ifdef __cplusplus
144}
145#endif
146
147#endif /* BOARD_H */
Native CPU peripheral configuration.