CPU specific configuration options. More...

Detailed Description

CPU specific configuration options.

Author: Koen Zandberg koen@.nosp@m.berg.nosp@m.zand..nosp@m.net

Definition in file cpu_conf.h.

#include "vendor/gd32vf103_core.h"
#include "cpu_conf_common.h"

Include dependency graph for cpu_conf.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros
#define	CONFIG_AFIO_PCF0_SWJ_CFG SWJ_CFG_NO_NJTRST
	By default, enable JTAG but disable NJTRST.

Enumerations
enum	afio_pcf0_swj_cfg_t { SWJ_CFG_FULL_JTAG = 0 , SWJ_CFG_NO_NJTRST = 1U << AFIO_PCF0_SWJ_CFG_Pos , SWJ_CFG_NO_JTAG = 4U << AFIO_PCF0_SWJ_CFG_Pos }
	Possible values of the `SWJ_CFG` field in the AFIO->PCF0 register. More...

#define	CLIC_NUM_INTERRUPTS (ECLIC_NUM_INTERRUPTS)

#define	CLIC_BASE_ADDR (ECLIC_CTRL_ADDR)

#define	CPU_DEFAULT_IRQ_PRIO (0xFF)

#define	HAVE_CSR_MIE (0)
	The gd32v doesn't use the MIE CSR, but uses the CLIC instead.

Flashpage settings
#define	FLASHPAGE_SIZE (1024U)

#define	FLASHPAGE_NUMOF (128U)

#define	FLASHPAGE_WRITE_BLOCK_SIZE (2U)

#define	FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)

#define	CPU_FLASH_BASE 0x08000000

Macro Definition Documentation

◆ CLIC_BASE_ADDR

#define CLIC_BASE_ADDR (ECLIC_CTRL_ADDR)

Definition at line 30 of file cpu_conf.h.

◆ CLIC_NUM_INTERRUPTS

#define CLIC_NUM_INTERRUPTS (ECLIC_NUM_INTERRUPTS)

Definition at line 29 of file cpu_conf.h.

◆ CONFIG_AFIO_PCF0_SWJ_CFG

#define CONFIG_AFIO_PCF0_SWJ_CFG SWJ_CFG_NO_NJTRST

By default, enable JTAG but disable NJTRST.

This default makes PB4 usable as GPIO while still being able to debug and flash via JTAG.

Definition at line 74 of file cpu_conf.h.

◆ CPU_DEFAULT_IRQ_PRIO

#define CPU_DEFAULT_IRQ_PRIO (0xFF)

Definition at line 31 of file cpu_conf.h.

◆ CPU_FLASH_BASE

#define CPU_FLASH_BASE 0x08000000

Definition at line 46 of file cpu_conf.h.

◆ FLASHPAGE_NUMOF

#define FLASHPAGE_NUMOF (128U)

Definition at line 43 of file cpu_conf.h.

◆ FLASHPAGE_SIZE

#define FLASHPAGE_SIZE (1024U)

Definition at line 42 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_ALIGNMENT

#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)

Definition at line 45 of file cpu_conf.h.

◆ FLASHPAGE_WRITE_BLOCK_SIZE

#define FLASHPAGE_WRITE_BLOCK_SIZE (2U)

Definition at line 44 of file cpu_conf.h.

◆ HAVE_CSR_MIE

#define HAVE_CSR_MIE (0)

The gd32v doesn't use the MIE CSR, but uses the CLIC instead.

Definition at line 36 of file cpu_conf.h.

Enumeration Type Documentation

◆ afio_pcf0_swj_cfg_t

enum afio_pcf0_swj_cfg_t

Possible values of the SWJ_CFG field in the AFIO->PCF0 register.

Enumerator
SWJ_CFG_FULL_JTAG	Full JTAG interface (reset value)
SWJ_CFG_NO_NJTRST	JTAG enabled, but NJTRST disabled and pin PB4 usable as GPIO.
SWJ_CFG_NO_JTAG	JTAG disabled, all debug pins usable as GPIOs.

Definition at line 52 of file cpu_conf.h.