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board.h
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "board_common.h"
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#include "
periph_conf.h
"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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#define LED0_PIN GPIO_PIN(PORT_B, 0)
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#define LED0_MASK (1 << 0)
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#define LED0_ON (GPIOB->PCOR = LED0_MASK)
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#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
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#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
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#define LED1_PIN GPIO_PIN(PORT_C, 1)
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#define LED1_MASK (1 << 1)
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#define LED1_ON (GPIOC->PCOR = LED1_MASK)
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#define LED1_OFF (GPIOC->PSOR = LED1_MASK)
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#define LED1_TOGGLE (GPIOC->PTOR = LED1_MASK)
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#define LED2_PIN GPIO_PIN(PORT_A, 19)
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#define LED2_MASK (1 << 19)
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#define LED2_ON (GPIOA->PCOR = LED2_MASK)
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#define LED2_OFF (GPIOA->PSOR = LED2_MASK)
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#define LED2_TOGGLE (GPIOA->PTOR = LED2_MASK)
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#define LED3_PIN GPIO_PIN(PORT_A, 18)
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#define LED3_MASK (1 << 18)
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#define LED3_ON (GPIOA->PCOR = LED3_MASK)
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#define LED3_OFF (GPIOA->PSOR = LED3_MASK)
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#define LED3_TOGGLE (GPIOA->PTOR = LED3_MASK)
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/* SW3, SW4 will short these pins to ground when pushed but there are no
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* external pull resistors, use internal pull-ups on the pins */
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/* BTN0 is mapped to SW3 */
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#define BTN0_PIN GPIO_PIN(PORT_C, 4)
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#define BTN0_MODE GPIO_IN_PU
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/* BTN1 is mapped to SW4 */
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#define BTN1_PIN GPIO_PIN(PORT_C, 5)
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#define BTN1_MODE GPIO_IN_PU
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#if IS_ACTIVE(KINETIS_XTIMER_SOURCE_PIT)
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/* PIT xtimer configuration */
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#define XTIMER_DEV (TIMER_PIT_DEV(0))
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#define XTIMER_CHAN (0)
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/* Default xtimer settings should work on the PIT */
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#else
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/* LPTMR xtimer configuration */
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#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
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#define XTIMER_CHAN (0)
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/* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
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#define XTIMER_WIDTH (16)
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#define XTIMER_BACKOFF (5)
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#define XTIMER_ISR_BACKOFF (5)
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#define XTIMER_HZ (32768ul)
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#endif
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#define CONFIG_ZTIMER_USEC_TYPE ZTIMER_TYPE_PERIPH_TIMER
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#define CONFIG_ZTIMER_USEC_DEV (TIMER_PIT_DEV(0))
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#define FRDM_NOR_SPI_DEV SPI_DEV(0)
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#define FRDM_NOR_SPI_CLK SPI_CLK_5MHZ
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#define FRDM_NOR_SPI_CS SPI_HWCS(0)
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#define FXOS8700_PARAM_I2C I2C_DEV(0)
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#define FXOS8700_PARAM_ADDR 0x1F
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#ifdef __cplusplus
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}
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#endif
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#endif
/* BOARD_H */
periph_conf.h
Native CPU peripheral configuration.
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