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board.h
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1/*
2 * Copyright (C) 2014 Freie Universität Berlin
3 * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser General
6 * Public License v2.1. See the file LICENSE in the top level directory for more
7 * details.
8 */
9
20#ifndef BOARD_H
21#define BOARD_H
22
23#include "cpu.h"
24#include "periph_conf.h"
25
26#ifdef __cplusplus
27extern "C"
28{
29#endif
30
35#define LED0_PIN GPIO_PIN(PORT_B, 22)
36#define LED1_PIN GPIO_PIN(PORT_E, 26)
37#define LED2_PIN GPIO_PIN(PORT_B, 21)
38
39#define LED0_MASK (1 << 22)
40#define LED1_MASK (1 << 26)
41#define LED2_MASK (1 << 21)
42
43#define LED0_ON (GPIOB->PCOR = LED0_MASK)
44#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
45#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
46
47#define LED1_ON (GPIOE->PCOR = LED1_MASK)
48#define LED1_OFF (GPIOE->PSOR = LED1_MASK)
49#define LED1_TOGGLE (GPIOE->PTOR = LED1_MASK)
50
51#define LED2_ON (GPIOB->PCOR = LED2_MASK)
52#define LED2_OFF (GPIOB->PSOR = LED2_MASK)
53#define LED2_TOGGLE (GPIOB->PTOR = LED2_MASK)
60/* SW2, SW3 will short these pins to ground when pushed. PTA4 has an external
61 * pull-up resistor to VDD, but there is no external pull resistor on PTC6 */
62/* BTN0 is mapped to SW2 */
63#define BTN0_PIN GPIO_PIN(PORT_C, 6)
64#define BTN0_MODE GPIO_IN_PU
65/* BTN1 is mapped to SW3 */
66#define BTN1_PIN GPIO_PIN(PORT_A, 4)
67#define BTN1_MODE GPIO_IN_PU
74#define FXOS8700_PARAM_I2C I2C_DEV(0)
75#define FXOS8700_PARAM_ADDR 0x1E
78#ifdef __cplusplus
79}
80#endif
81
82#endif /* BOARD_H */
Native CPU peripheral configuration.