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cfg_usb_otg_hs_phy_utmi.h
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1/*
2 * SPDX-FileCopyrightText: 2019 Koen Zandberg
3 * SPDX-FileCopyrightText: 2022 Gunar Schorcht
4 * SPDX-License-Identifier: LGPL-2.1-only
5 */
6
7#pragma once
8
23
24#include "periph_cpu.h"
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
34#define DWC2_USB_OTG_HS_ENABLED
35
36#ifndef USBPHYC_TUNE_VALUE
50#define USBPHYC_TUNE_VALUE 0x00000f13U
51#endif
52
57 {
58 .periph = USB_OTG_HS_PERIPH_BASE,
59 .type = DWC2_USB_OTG_HS,
61 .rcc_mask = RCC_AHB1ENR_OTGHSEN,
62 .irqn = OTG_HS_IRQn,
63 .ahb = AHB1,
64 .dm = GPIO_PIN(PORT_B, 14),
65 .dp = GPIO_PIN(PORT_B, 15),
66 .af = GPIO_AF10,
67 .phy_tune = USBPHYC_TUNE_VALUE,
68 }
69};
70
74#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
75
76#ifdef __cplusplus
77}
78#endif
79
@ PORT_B
port B
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:45
#define USBPHYC_TUNE_VALUE
Default value of USBPHYC tuning control register.
@ GPIO_AF10
use alternate function 10
Definition cpu_gpio.h:112
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[]
Common USB OTG FS configuration.
Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core.
@ DWC2_USB_OTG_PHY_UTMI
UTMI for internal HS PHY.
@ DWC2_USB_OTG_HS
High speed peripheral.