Bank configuration structure for SDRAM. More...

Detailed Description

Bank configuration structure for SDRAM.

Definition at line 238 of file cpu_fmc.h.

#include <cpu_fmc.h>

Data Fields
uint8_t	clk_period
	CLK period [0,2,3] (0 - disabled, n * HCLK cycles)

uint8_t	row_bits
	Number row address bits [11..13].

uint8_t	col_bits
	Number column address bits [8..11].

uint8_t	cas_latency
	CAS latency in SDCLK clock cycles [1..3].

uint8_t	read_delay
	Delay for reading data after CAS latency in HCLKs [0..2].

bool	four_banks
	SDRAM has four internal banks.

bool	write_protect
	Write protection enabled.

bool	burst_read
	Burst read mode enabled.

bool	burst_write
	Burst write mode enabled.

bool	burst_interleaved
	Burst mode interleaved, otherwise sequential.

fmc_bust_length_t	burst_len
	Burst length as an exponent of a power of two.

fmc_sdram_timing_t	timing
	SDRAM Timing configuration.

Field Documentation

◆ burst_interleaved

bool fmc_sdram_bank_conf_t::burst_interleaved

Burst mode interleaved, otherwise sequential.

Definition at line 248 of file cpu_fmc.h.

◆ burst_len

fmc_bust_length_t fmc_sdram_bank_conf_t::burst_len

Burst length as an exponent of a power of two.

Definition at line 249 of file cpu_fmc.h.

◆ burst_read

bool fmc_sdram_bank_conf_t::burst_read

Burst read mode enabled.

Definition at line 246 of file cpu_fmc.h.

◆ burst_write

bool fmc_sdram_bank_conf_t::burst_write

Burst write mode enabled.

Definition at line 247 of file cpu_fmc.h.

◆ cas_latency

uint8_t fmc_sdram_bank_conf_t::cas_latency

CAS latency in SDCLK clock cycles [1..3].

Definition at line 242 of file cpu_fmc.h.

◆ clk_period

uint8_t fmc_sdram_bank_conf_t::clk_period

CLK period [0,2,3] (0 - disabled, n * HCLK cycles)

Definition at line 239 of file cpu_fmc.h.

◆ col_bits

uint8_t fmc_sdram_bank_conf_t::col_bits

Number column address bits [8..11].

Definition at line 241 of file cpu_fmc.h.

◆ four_banks

bool fmc_sdram_bank_conf_t::four_banks

SDRAM has four internal banks.

Definition at line 244 of file cpu_fmc.h.

◆ read_delay

uint8_t fmc_sdram_bank_conf_t::read_delay

Delay for reading data after CAS latency in HCLKs [0..2].

Definition at line 243 of file cpu_fmc.h.

◆ row_bits

uint8_t fmc_sdram_bank_conf_t::row_bits

Number row address bits [11..13].

Definition at line 240 of file cpu_fmc.h.

◆ timing

fmc_sdram_timing_t fmc_sdram_bank_conf_t::timing

SDRAM Timing configuration.

Definition at line 250 of file cpu_fmc.h.

◆ write_protect

bool fmc_sdram_bank_conf_t::write_protect

Write protection enabled.

Definition at line 245 of file cpu_fmc.h.

The documentation for this struct was generated from the following file:

cpu/stm32/include/periph/cpu_fmc.h