Ethernet CPU specific definitions for the STM32 family.
More...
#include <stdint.h>
#include "periph/cpu_gpio.h"
Go to the source code of this file.
|
| #define | RX_DESC_CTRL_RCH (BIT14) |
| | Indicates if RDES3 points to the next DMA descriptor (1), or to a second buffer (0)
|
| |
|
| #define | TX_DESC_STAT_UF (BIT1) |
| | If set, an underflow occurred while sending.
|
| |
| #define | TX_DESC_STAT_EC (BIT8) |
| | If set, TX was aborted due to excessive collisions (half-duplex only)
|
| |
| #define | TX_DESC_STAT_NC (BIT10) |
| | If set, no carrier was detected (TX aborted)
|
| |
| #define | TX_DESC_STAT_ES (BIT15) |
| | If set, one or more error occurred.
|
| |
| #define | TX_DESC_STAT_TTSS (BIT17) |
| | If set, the descriptor contains a valid PTP timestamp.
|
| |
| #define | TX_DESC_STAT_TCH (BIT20) |
| | Indicates if TDES3 points to the next DMA descriptor (1), or to a second buffer (0)
|
| |
| #define | TX_DESC_STAT_TER (BIT21) |
| | If set, DMA will return to first descriptor in ring afterwards.
|
| |
| #define | TX_DESC_STAT_CIC (BIT22 | BIT23) |
| | Checksum insertion control.
|
| |
| #define | TX_DESC_STAT_TTSE (BIT25) |
| | If set, an PTP timestamp is added to the descriptor after TX completed.
|
| |
| #define | TX_DESC_STAT_FS (BIT28) |
| | If set, buffer contains first segment of frame to transmit.
|
| |
| #define | TX_DESC_STAT_LS (BIT29) |
| | If set, buffer contains last segment of frame to transmit.
|
| |
| #define | TX_DESC_STAT_IC (BIT30) |
| | If set, trigger IRQ on completion.
|
| |
| #define | TX_DESC_STAT_OWN (BIT31) |
| | If set, descriptor is owned by DMA, otherwise by CPU.
|
| |
| enum | eth_mode_t { MII = 18
, RMII = 9
, SMI = 2
} |
| | STM32 Ethernet configuration mode. More...
|
| |
| typedef struct eth_dma_desc | edma_desc_t |
| | Layout of enhanced RX/TX DMA descriptor.
|
| |
◆ RX_DESC_CTRL_RCH
| #define RX_DESC_CTRL_RCH (BIT14) |
Indicates if RDES3 points to the next DMA descriptor (1), or to a second buffer (0)
If the bit is set, RDES3 (edma_desc_t::desc_next) will point to the next DMA descriptor rather than to a second frame-segment buffer. This is always set by the driver
Definition at line 113 of file cpu_eth.h.
◆ RX_DESC_STAT_DE
| #define RX_DESC_STAT_DE (BIT14) |
If set, a frame too large to fit buffers given by descriptors was received.
Definition at line 98 of file cpu_eth.h.
◆ RX_DESC_STAT_ES
| #define RX_DESC_STAT_ES (BIT14) |
If set, an error occurred during RX.
Definition at line 99 of file cpu_eth.h.
◆ RX_DESC_STAT_FL
| #define RX_DESC_STAT_FL (0x3FFF0000) /* bits 16-29 */ |
◆ RX_DESC_STAT_FS
| #define RX_DESC_STAT_FS (BIT9) |
If set, descriptor is the first of a frame.
Definition at line 90 of file cpu_eth.h.
◆ RX_DESC_STAT_LS
| #define RX_DESC_STAT_LS (BIT8) |
If set, descriptor is the last of a frame.
Definition at line 89 of file cpu_eth.h.
◆ RX_DESC_STAT_OWN
| #define RX_DESC_STAT_OWN (BIT31) |
If set, descriptor is owned by DMA, otherwise by CPU.
Definition at line 100 of file cpu_eth.h.
◆ TX_DESC_STAT_CIC
Checksum insertion control.
| Value | Meaning |
0b00 | Checksum insertion disabled |
0b01 | Calculate and insert checksum in IPv4 header |
0b10 | Calculate and insert IPv4 checksum, insert pre-calculated payload checksum |
| `0b11 | Calculated and insert both IPv4 and payload checksum |
Definition at line 143 of file cpu_eth.h.
◆ TX_DESC_STAT_EC
| #define TX_DESC_STAT_EC (BIT8) |
If set, TX was aborted due to excessive collisions (half-duplex only)
Definition at line 120 of file cpu_eth.h.
◆ TX_DESC_STAT_ES
| #define TX_DESC_STAT_ES (BIT15) |
If set, one or more error occurred.
Definition at line 122 of file cpu_eth.h.
◆ TX_DESC_STAT_FS
| #define TX_DESC_STAT_FS (BIT28) |
If set, buffer contains first segment of frame to transmit.
Definition at line 145 of file cpu_eth.h.
◆ TX_DESC_STAT_IC
| #define TX_DESC_STAT_IC (BIT30) |
If set, trigger IRQ on completion.
Definition at line 147 of file cpu_eth.h.
◆ TX_DESC_STAT_LS
| #define TX_DESC_STAT_LS (BIT29) |
If set, buffer contains last segment of frame to transmit.
Definition at line 146 of file cpu_eth.h.
◆ TX_DESC_STAT_NC
| #define TX_DESC_STAT_NC (BIT10) |
If set, no carrier was detected (TX aborted)
Definition at line 121 of file cpu_eth.h.
◆ TX_DESC_STAT_OWN
| #define TX_DESC_STAT_OWN (BIT31) |
If set, descriptor is owned by DMA, otherwise by CPU.
Definition at line 148 of file cpu_eth.h.
◆ TX_DESC_STAT_TCH
| #define TX_DESC_STAT_TCH (BIT20) |
Indicates if TDES3 points to the next DMA descriptor (1), or to a second buffer (0)
If the bit is set, TDES3 (edma_desc_t::desc_next) will point to the next DMA descriptor rather than to a second frame-segment buffer. This is always set by the driver
Definition at line 131 of file cpu_eth.h.
◆ TX_DESC_STAT_TER
| #define TX_DESC_STAT_TER (BIT21) |
If set, DMA will return to first descriptor in ring afterwards.
Definition at line 132 of file cpu_eth.h.
◆ TX_DESC_STAT_TTSE
| #define TX_DESC_STAT_TTSE (BIT25) |
If set, an PTP timestamp is added to the descriptor after TX completed.
Definition at line 144 of file cpu_eth.h.
◆ TX_DESC_STAT_TTSS
| #define TX_DESC_STAT_TTSS (BIT17) |
If set, the descriptor contains a valid PTP timestamp.
Definition at line 123 of file cpu_eth.h.
◆ TX_DESC_STAT_UF
| #define TX_DESC_STAT_UF (BIT1) |
If set, an underflow occurred while sending.
Definition at line 119 of file cpu_eth.h.
◆ edma_desc_t
Layout of enhanced RX/TX DMA descriptor.
- Note
- Don't confuse this with the normal RX/TX descriptor format.
- Warning
- The content of the status and control bits is different for RX and TX DMA descriptors
◆ eth_mode_t
STM32 Ethernet configuration mode.
| Enumerator |
|---|
| MII | Configuration for MII.
|
| RMII | Configuration for RMII.
|
| SMI | Configuration for SMI.
|
Definition at line 35 of file cpu_eth.h.
Include dependency graph for cpu_eth.h: