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periph_conf.h
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1/*
2 * Copyright (C) 2015 Hamburg University of Applied Sciences
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22#include "periph_cpu.h"
23#include "clk_conf.h"
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
33static const timer_conf_t timer_config[] = {
34 {
35 .dev = TIM5,
36 .max = 0x0000ffff,
37 .rcc_mask = RCC_APB1ENR_TIM5EN,
38 .bus = APB1,
39 .irqn = TIM5_IRQn
40 }
41};
42
43#define TIMER_0_ISR (isr_tim5)
44
45#define TIMER_NUMOF ARRAY_SIZE(timer_config)
52static const uart_conf_t uart_config[] = {
53 {
54 .dev = USART3,
55 .rcc_mask = RCC_APB1ENR_USART3EN,
56 .rx_pin = GPIO_PIN(PORT_C, 11),
57 .tx_pin = GPIO_PIN(PORT_C, 10),
58 .rx_af = GPIO_AF7,
59 .tx_af = GPIO_AF7,
60 .bus = APB1,
61 .irqn = USART3_IRQn
62 },
63 {
64 .dev = USART1,
65 .rcc_mask = RCC_APB2ENR_USART1EN,
66 .rx_pin = GPIO_PIN(PORT_A, 10),
67 .tx_pin = GPIO_PIN(PORT_A, 9),
68 .rx_af = GPIO_AF7,
69 .tx_af = GPIO_AF7,
70 .bus = APB2,
71 .irqn = USART1_IRQn
72 }
73};
74
75#define UART_0_ISR (isr_usart3)
76#define UART_1_ISR (isr_usart1)
77
78#define UART_NUMOF ARRAY_SIZE(uart_config)
85static const spi_conf_t spi_config[] = {
86 {
87 .dev = SPI1,
88 .mosi_pin = GPIO_PIN(PORT_A, 7),
89 .miso_pin = GPIO_PIN(PORT_A, 6),
90 .sclk_pin = GPIO_PIN(PORT_A, 5),
91 .cs_pin = SPI_CS_UNDEF,
92 .mosi_af = GPIO_AF5,
93 .miso_af = GPIO_AF5,
94 .sclk_af = GPIO_AF5,
95 .cs_af = GPIO_AF5,
96 .rccmask = RCC_APB2ENR_SPI1EN,
97 .apbbus = APB2
98 },
99 {
100 .dev = SPI3,
101 .mosi_pin = GPIO_PIN(PORT_B, 5),
102 .miso_pin = GPIO_PIN(PORT_B, 4),
103 .sclk_pin = GPIO_PIN(PORT_B, 3),
104 .cs_pin = SPI_CS_UNDEF,
105 .mosi_af = GPIO_AF6,
106 .miso_af = GPIO_AF6,
107 .sclk_af = GPIO_AF6,
108 .cs_af = GPIO_AF6,
109 .rccmask = RCC_APB1ENR_SPI3EN,
110 .apbbus = APB1
111 }
112};
113
114#define SPI_NUMOF ARRAY_SIZE(spi_config)
121static const i2c_conf_t i2c_config[] = {
122 {
123 .dev = I2C1,
124 .speed = I2C_SPEED_NORMAL,
125 .scl_pin = GPIO_PIN(PORT_B, 8),
126 .sda_pin = GPIO_PIN(PORT_B, 9),
127 .scl_af = GPIO_AF4,
128 .sda_af = GPIO_AF4,
129 .bus = APB1,
130 .rcc_mask = RCC_APB1ENR_I2C1EN,
131 .clk = CLOCK_APB1,
132 .irqn = I2C1_EV_IRQn
133 },
134 {
135 .dev = I2C2,
136 .speed = I2C_SPEED_NORMAL,
137 .scl_pin = GPIO_PIN(PORT_B, 10),
138 .sda_pin = GPIO_PIN(PORT_B, 11),
139 .scl_af = GPIO_AF4,
140 .sda_af = GPIO_AF4,
141 .bus = APB1,
142 .rcc_mask = RCC_APB1ENR_I2C2EN,
143 .clk = CLOCK_APB1,
144 .irqn = I2C2_EV_IRQn
145 }
146};
147
148#define I2C_0_ISR isr_i2c1_ev
149#define I2C_1_ISR isr_i2c2_ev
150
151#define I2C_NUMOF ARRAY_SIZE(i2c_config)
154#ifdef __cplusplus
155}
156#endif
157
158#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_C
port C
Definition periph_cpu.h:49
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF4
use alternate function 4
Definition cpu_gpio.h:106
@ GPIO_AF6
use alternate function 6
Definition cpu_gpio.h:108
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
I2C configuration structure.
Definition periph_cpu.h:299
TWI_t * dev
Pointer to hardware module registers.
Definition periph_cpu.h:300
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219