periph_conf.h
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1 /*
2  * Copyright (C) 2015 Hamburg University of Applied Sciences
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSI (16000000U) /* internal oscillator */
33 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
34 
35 /* configuration of PLL prescaler and multiply values */
36 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
37 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
38 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
39 /* configuration of peripheral bus clock prescalers */
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
43 /* configuration of flash access cycles */
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM5,
59  .max = 0x0000ffff,
60  .rcc_mask = RCC_APB1ENR_TIM5EN,
61  .bus = APB1,
62  .irqn = TIM5_IRQn
63  }
64 };
65 
66 #define TIMER_0_ISR (isr_tim5)
67 
68 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
69 
75 static const uart_conf_t uart_config[] = {
76  {
77  .dev = USART3,
78  .rcc_mask = RCC_APB1ENR_USART3EN,
79  .rx_pin = GPIO_PIN(PORT_C, 11),
80  .tx_pin = GPIO_PIN(PORT_C, 10),
81  .rx_af = GPIO_AF7,
82  .tx_af = GPIO_AF7,
83  .bus = APB1,
84  .irqn = USART3_IRQn
85  },
86  {
87  .dev = USART1,
88  .rcc_mask = RCC_APB2ENR_USART1EN,
89  .rx_pin = GPIO_PIN(PORT_A, 10),
90  .tx_pin = GPIO_PIN(PORT_A, 9),
91  .rx_af = GPIO_AF7,
92  .tx_af = GPIO_AF7,
93  .bus = APB2,
94  .irqn = USART1_IRQn
95  }
96 };
97 
98 #define UART_0_ISR (isr_usart3)
99 #define UART_1_ISR (isr_usart1)
100 
101 #define UART_NUMOF ARRAY_SIZE(uart_config)
102 
111 static const uint8_t spi_divtable[2][5] = {
112  { /* for APB1 @ 32000000Hz */
113  7, /* -> 125000Hz */
114  5, /* -> 500000Hz */
115  4, /* -> 1000000Hz */
116  2, /* -> 4000000Hz */
117  1 /* -> 8000000Hz */
118  },
119  { /* for APB2 @ 32000000Hz */
120  7, /* -> 125000Hz */
121  5, /* -> 500000Hz */
122  4, /* -> 1000000Hz */
123  2, /* -> 4000000Hz */
124  1 /* -> 8000000Hz */
125  }
126 };
127 
128 static const spi_conf_t spi_config[] = {
129  {
130  .dev = SPI1,
131  .mosi_pin = GPIO_PIN(PORT_A, 7),
132  .miso_pin = GPIO_PIN(PORT_A, 6),
133  .sclk_pin = GPIO_PIN(PORT_A, 5),
134  .cs_pin = GPIO_UNDEF,
135  .mosi_af = GPIO_AF5,
136  .miso_af = GPIO_AF5,
137  .sclk_af = GPIO_AF5,
138  .cs_af = GPIO_AF5,
139  .rccmask = RCC_APB2ENR_SPI1EN,
140  .apbbus = APB2
141  },
142  {
143  .dev = SPI3,
144  .mosi_pin = GPIO_PIN(PORT_B, 5),
145  .miso_pin = GPIO_PIN(PORT_B, 4),
146  .sclk_pin = GPIO_PIN(PORT_B, 3),
147  .cs_pin = GPIO_UNDEF,
148  .mosi_af = GPIO_AF6,
149  .miso_af = GPIO_AF6,
150  .sclk_af = GPIO_AF6,
151  .cs_af = GPIO_AF6,
152  .rccmask = RCC_APB1ENR_SPI3EN,
153  .apbbus = APB1
154  }
155 };
156 
157 #define SPI_NUMOF ARRAY_SIZE(spi_config)
158 
164 static const i2c_conf_t i2c_config[] = {
165  {
166  .dev = I2C1,
167  .speed = I2C_SPEED_NORMAL,
168  .scl_pin = GPIO_PIN(PORT_B, 8),
169  .sda_pin = GPIO_PIN(PORT_B, 9),
170  .scl_af = GPIO_AF4,
171  .sda_af = GPIO_AF4,
172  .bus = APB1,
173  .rcc_mask = RCC_APB1ENR_I2C1EN,
174  .clk = CLOCK_APB1,
175  .irqn = I2C1_EV_IRQn
176  },
177  {
178  .dev = I2C2,
179  .speed = I2C_SPEED_NORMAL,
180  .scl_pin = GPIO_PIN(PORT_B, 10),
181  .sda_pin = GPIO_PIN(PORT_B, 11),
182  .scl_af = GPIO_AF4,
183  .sda_af = GPIO_AF4,
184  .bus = APB1,
185  .rcc_mask = RCC_APB1ENR_I2C2EN,
186  .clk = CLOCK_APB1,
187  .irqn = I2C2_EV_IRQn
188  }
189 };
190 
191 #define I2C_0_ISR isr_i2c1_ev
192 #define I2C_1_ISR isr_i2c2_ev
193 
194 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
195 
197 #ifdef __cplusplus
198 }
199 #endif
200 
201 #endif /* PERIPH_CONF_H */
202 
port C
Definition: periph_cpu.h:38
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
APB1 bus.
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
NRF_TIMER_Type * dev
timer device
use alternate function 5
use alternate function 6
port A
Definition: periph_cpu.h:36
use alternate function 4
APB2 bus.
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:161
SPI configuration structure type.
Definition: periph_cpu.h:273
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
Timer configuration.
Definition: periph_cpu.h:288
use alternate function 7
port B
Definition: periph_cpu.h:37