Loading...
Searching...
No Matches
board.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2018 HAW Hamburg
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
22#ifndef BOARD_H
23#define BOARD_H
24
25#include "cpu.h"
26#include "periph_conf.h"
27#include "periph_cpu.h"
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
37#define LED0_PIN GPIO_PIN(PA, 27)
38
39#define LED_PORT PORT->Group[PA]
40#define LED0_MASK (1 << 27)
41
42#define LED0_ON (LED_PORT.OUTSET.reg = LED0_MASK)
43#define LED0_OFF (LED_PORT.OUTCLR.reg = LED0_MASK)
44#define LED0_TOGGLE (LED_PORT.OUTTGL.reg = LED0_MASK)
45
46#define LED1_PIN GPIO_PIN(PA, 28)
47#define LED1_MASK (1 << 28)
48
49#define LED1_ON (LED_PORT.OUTSET.reg = LED1_MASK)
50#define LED1_OFF (LED_PORT.OUTCLR.reg = LED1_MASK)
51#define LED1_TOGGLE (LED_PORT.OUTTGL.reg = LED1_MASK)
58#define BTN0_PIN GPIO_PIN(PA, 20)
59#define BTN0_MODE GPIO_IN_PU
69#define XBEE1_EN_PORT PORT->Group[PB]
70#define XBEE1_EN_MASK (1 << 3)
71#define XBEE1_EN_MODE GPIO_OUT
72#define XBEE1_EN_PIN GPIO_PIN(PB, 3)
73
74#define XBEE1_ENABLE (XBEE1_EN_PORT.OUTCLR.reg = XBEE1_EN_MASK)
75#define XBEE1_DISABLE (XBEE1_EN_PORT.OUTSET.reg = XBEE1_EN_MASK)
76
77#define XBEE1_CS_PIN GPIO_PIN(PA, 18)
78
79#define XBEE1_INT_PIN GPIO_PIN(PA, 21)
89#define XBEE2_EN_PORT PORT->Group[PB]
90#define XBEE2_EN_MASK (1 << 10)
91#define XBEE2_EN_PIN GPIO_PIN(PB, 10)
92#define XBEE2_EN_MODE GPIO_OUT
93
94#define XBEE2_ENABLE (XBEE2_EN_PORT.OUTCLR.reg = XBEE2_EN_MASK)
95#define XBEE2_DISABLE (XBEE2_EN_PORT.OUTSET.reg = XBEE2_EN_MASK)
96
97#define XBEE2_CS_PIN GPIO_PIN(PA, 14)
98
99#define XBEE2_INT_PIN GPIO_PIN(PA, 15)
109#define I2C_EN_PORT PORT->Group[PB]
110#define I2C_EN_MASK (1 << 11)
111#define I2C_EN_PIN GPIO_PIN(PB, 11)
112#define I2C_EN_MODE GPIO_OUT
113
114#define I2C_ENABLE (I2C_EN_PORT.OUTSET.reg = I2C_EN_MASK)
115#define I2C_DISABLE (I2C_EN_PORT.OUTCLR.reg = I2C_EN_MASK)
127#define SX127X_PARAM_SPI (SPI_DEV(0))
128
129#define SX127X_PARAM_SPI_NSS XBEE1_CS_PIN /* D23 */
130
131#define SX127X_PARAM_RESET GPIO_UNDEF
132
133#define SX127X_PARAM_DIO0 XBEE1_INT_PIN /* D24 */
134
135#define SX127X_PARAM_DIO1 GPIO_UNDEF
136
137#define SX127X_PARAM_DIO2 GPIO_UNDEF
138
139#define SX127X_PARAM_DIO3 GPIO_UNDEF
140
141#define SX127X_PARAM_PASELECT (SX127X_PA_BOOST)
147#define WAIT_FOR_SPI_RESET (3000000UL)
148
152#define HDC1000_PARAM_ADDR (0x40)
153
157#define TSL2561_PARAM_ADDR TSL2561_ADDR_LOW
158
162#define BMX280_PARAM_I2C_ADDR (0x76)
163
164#if defined(MODULE_MTD_SDCARD) || defined(DOXYGEN)
169#define MTD_0 mtd_dev_get(0)
171#endif /* MODULE_MTD_SDCARD || DOXYGEN */
172
173#ifdef __cplusplus
174}
175#endif
176
177#endif /* BOARD_H */
Native CPU peripheral configuration.