periph_cpu.h File Reference

nRF52 specific definitions for handling peripherals More...

Detailed Description

nRF52 specific definitions for handling peripherals

Author

Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

Philipp-Alexander Blum phili.nosp@m.pp-b.nosp@m.lum@j.nosp@m.akik.nosp@m.u.de

Definition in file periph_cpu.h.

#include "periph_cpu_common.h"

Include dependency graph for periph_cpu.h:

Go to the source code of this file.

Data Structures
struct	i2c_conf_t
	I2C configuration structure. More...
struct	pwm_conf_t
	PWM device configuration. More...
struct	uart_conf_t
	UART device configuration. More...
struct	spi_conf_t
	SPI device configuration. More...

Macros
#define	ADC_NUMOF   (9U)
	The nRF52 family of CPUs provides a fixed number of 9 ADC lines.
#define	CONFIG_SPI_MBUF_SIZE   64
	SPI temporary buffer size for storing const data in RAM before initiating DMA transfer.
#define	UART_TXBUF_SIZE   (64)
	Size of the UART TX buffer for non-blocking mode.
#define	USBDEV_CPU_DMA_ALIGNMENT   (4)
	USBDEV buffers must be word aligned because of DMA restrictions.
#define	USBDEV_CPU_DMA_REQUIREMENTS   __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
	USBDEV buffer instantiation requirement.

Typedefs
typedef void(*	spi_twi_irq_cb_t) (void *arg)
	Common SPI/I2C interrupt callback. More...

Enumerations
enum	{   NRF52_AIN0 = 0 , NRF52_AIN1 = 1 , NRF52_AIN2 = 2 , NRF52_AIN3 = 3 ,   NRF52_AIN4 = 4 , NRF52_AIN5 = 5 , NRF52_AIN6 = 6 , NRF52_AIN7 = 7 ,   NRF52_VDD = 8 }
	nRF52 specific naming of ADC lines (for convenience) More...

Functions
void	spi_twi_irq_register_spi (NRF_SPIM_Type *bus, spi_twi_irq_cb_t cb, void *arg)
	Register a SPI IRQ handler for a shared I2C/SPI irq vector. More...
void	spi_twi_irq_register_i2c (NRF_TWIM_Type *bus, spi_twi_irq_cb_t cb, void *arg)
	Register a I2C IRQ handler for a shared I2C/SPI irq vector. More...
void	nrf5x_i2c_acquire (NRF_TWIM_Type *bus, spi_twi_irq_cb_t cb, void *arg)
	Acquire the shared I2C/SPI peripheral in I2C mode. More...
void	nrf5x_i2c_release (NRF_TWIM_Type *bus)
	Release the shared I2C/SPI peripheral in I2C mode. More...
void	nrf5x_spi_acquire (NRF_SPIM_Type *bus, spi_twi_irq_cb_t cb, void *arg)
	Acquire the shared I2C/SPI peripheral in SPI mode. More...
void	nrf5x_spi_release (NRF_SPIM_Type *bus)
	Acquire the shared I2C/SPI peripheral in SPI mode. More...
#define	CLOCK_CORECLOCK   (64000000U)
	Enable the workaround for the SPI single byte transmit errata (No. More...

Peripheral clock speed (fixed to 16MHz for nRF52 based CPUs)
#define	PERIPH_CLOCK   (16000000U)
#define	SPI_SCKSEL   (dev(bus)->PSEL.SCK)
	Redefine some peripheral names to unify them between nRF51 and 52.
#define	SPI_MOSISEL   (dev(bus)->PSEL.MOSI)
#define	SPI_MISOSEL   (dev(bus)->PSEL.MISO)

Define macros for sda and scl pin to be able to reinitialize them
#define	i2c_pin_sda(dev)   i2c_config[dev].sda
#define	i2c_pin_scl(dev)   i2c_config[dev].scl

The PWM unit on the nRF52 supports 4 channels per device
#define	PWM_CHANNELS   (4U)

Generate PWM mode values
To encode the PWM mode, we use two bit: bit 0: select up or up-and-down counting bit 15: select polarity
#define	PWM_MODE(ud, pol)   (ud | (pol << 15))
#define	HAVE_PWM_MODE_T
	Override the PWM mode definitions.
enum	pwm_mode_t {   PWM_LEFT = PWM_MODE(0, 1) , PWM_RIGHT = PWM_MODE(0, 0) , PWM_CENTER = PWM_MODE(1, 1) , PWM_CENTER_INV = PWM_MODE(1, 0) ,   PWM_LEFT = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK) , PWM_RIGHT = (TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK) , PWM_CENTER = (TPM_CnSC_MSB_MASK) , PWM_LEFT ,   PWM_RIGHT , PWM_CENTER }

Macro Definition Documentation

CLOCK_CORECLOCK

#define CLOCK_CORECLOCK   (64000000U)

Enable the workaround for the SPI single byte transmit errata (No.

58 on the nrf52832)

System core clock speed, fixed to 64MHz for all NRF52x CPUs

Definition at line 41 of file periph_cpu.h.

Typedef Documentation

spi_twi_irq_cb_t

typedef void(* spi_twi_irq_cb_t) (void *arg)

Common SPI/I2C interrupt callback.

Parameters

arg	Opaque context pointer

Definition at line 246 of file periph_cpu.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

nRF52 specific naming of ADC lines (for convenience)

Enumerator
NRF52_AIN0	Analog Input 0.
NRF52_AIN1	Analog Input 1.
NRF52_AIN2	Analog Input 2.
NRF52_AIN3	Analog Input 3.
NRF52_AIN4	Analog Input 4.
NRF52_AIN5	Analog Input 5.
NRF52_AIN6	Analog Input 6.
NRF52_AIN7	Analog Input 7.
NRF52_VDD	VDD, not useful if VDD is reference...

Definition at line 80 of file periph_cpu.h.

pwm_mode_t

enum pwm_mode_t

Enumerator
PWM_LEFT	left aligned PWM
PWM_RIGHT	right aligned PWM
PWM_CENTER	not supported
PWM_CENTER_INV	not supported
PWM_LEFT	left aligned
PWM_RIGHT	right aligned
PWM_CENTER	center aligned

Definition at line 175 of file periph_cpu.h.

Function Documentation

nrf5x_i2c_acquire()

void nrf5x_i2c_acquire	(	NRF_TWIM_Type *	bus,
		spi_twi_irq_cb_t	cb,
		void *	arg
	)

Acquire the shared I2C/SPI peripheral in I2C mode.

Parameters

bus	bus to acquire exclusive access on
cb	ISR handler to call on IRQ
arg	ISR handler argument

nrf5x_i2c_release()

void nrf5x_i2c_release

(

NRF_TWIM_Type *

bus

)

Release the shared I2C/SPI peripheral in I2C mode.

Parameters

bus	bus to release exclusive access on

nrf5x_spi_acquire()

void nrf5x_spi_acquire	(	NRF_SPIM_Type *	bus,
		spi_twi_irq_cb_t	cb,
		void *	arg
	)

Acquire the shared I2C/SPI peripheral in SPI mode.

Parameters

bus	bus to release exclusive access on
cb	ISR handler to call on IRQ
arg	ISR handler argument

nrf5x_spi_release()

void nrf5x_spi_release

(

NRF_SPIM_Type *

bus

)

Acquire the shared I2C/SPI peripheral in SPI mode.

Parameters

bus	bus to release exclusive access on

spi_twi_irq_register_i2c()

void spi_twi_irq_register_i2c	(	NRF_TWIM_Type *	bus,
		spi_twi_irq_cb_t	cb,
		void *	arg
	)

Register a I2C IRQ handler for a shared I2C/SPI irq vector.

Parameters

bus	bus to register the IRQ handler on
cb	callback to call on IRQ
arg	Argument to pass to the handler

spi_twi_irq_register_spi()

void spi_twi_irq_register_spi	(	NRF_SPIM_Type *	bus,
		spi_twi_irq_cb_t	cb,
		void *	arg
	)

Register a SPI IRQ handler for a shared I2C/SPI irq vector.

Parameters

bus	bus to register the IRQ handler on
cb	callback to call on IRQ
arg	Argument to pass to the handler