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board.h
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1/*
2 * Copyright (C) 2014 Eistec AB
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
9#pragma once
10
20
21#include "cpu.h"
22#include "periph_conf.h"
23#include "mulle-nvram.h"
24
25/* Use the on board RTC 32kHz clock for LPTMR clocking. */
26#undef LPTIMER_CLKSRC
28#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
29
31#define DISABLE_WDOG 1
32
36#define STDIO_UART_DEV UART_DEV(1)
37
42#if 0
43/* LPTMR xtimer configuration */
44/* WIP, Use PIT for now */
45#define XTIMER_DEV (TIMER_LPTMR_DEV(0))
46/* LPTMR is 16 bits wide */
47#define XTIMER_WIDTH (16)
48#define XTIMER_BACKOFF (4)
49#define XTIMER_ISR_BACKOFF (4)
50#define XTIMER_HZ (32768ul)
51#else
52/* PIT xtimer configuration */
53#define XTIMER_DEV (TIMER_PIT_DEV(0))
54#define XTIMER_CHAN (0)
55#define XTIMER_BACKOFF (40)
56#define XTIMER_ISR_BACKOFF (40)
57#endif
59
64#define LED_PORT PTC
65#define LED0_BIT (15)
66#define LED1_BIT (14)
67#define LED2_BIT (13)
68
69#define LED0_PIN GPIO_PIN(PORT_C, LED0_BIT)
70#define LED1_PIN GPIO_PIN(PORT_C, LED1_BIT)
71#define LED2_PIN GPIO_PIN(PORT_C, LED2_BIT)
72
73#define LED0_ON (LED_PORT->PSOR = (1 << LED0_BIT))
74#define LED0_OFF (LED_PORT->PCOR = (1 << LED0_BIT))
75#define LED0_TOGGLE (LED_PORT->PTOR = (1 << LED0_BIT))
76
77#define LED1_ON (LED_PORT->PSOR = (1 << LED1_BIT))
78#define LED1_OFF (LED_PORT->PCOR = (1 << LED1_BIT))
79#define LED1_TOGGLE (LED_PORT->PTOR = (1 << LED1_BIT))
80
81#define LED2_ON (LED_PORT->PSOR = (1 << LED2_BIT))
82#define LED2_OFF (LED_PORT->PCOR = (1 << LED2_BIT))
83#define LED2_TOGGLE (LED_PORT->PTOR = (1 << LED2_BIT))
85
86#ifdef __cplusplus
87extern "C" {
88#endif
89
90#ifdef __cplusplus
91}
92#endif
93
98
103#define AT86RF2XX_PARAM_CS SPI_HWCS(1)
104#define AT86RF2XX_PARAM_INT GPIO_PIN(PORT_B, 9)
105#define AT86RF2XX_PARAM_SLEEP GPIO_PIN(PORT_E, 6)
106#define AT86RF2XX_PARAM_RESET GPIO_PIN(PORT_C, 12)
108
113#define LIS3DH_PARAM_INT1 GPIO_PIN(PORT_C, 18)
114#define LIS3DH_PARAM_INT2 GPIO_PIN(PORT_C, 17)
115#define LIS3DH_PARAM_CS SPI_HWCS(0)
116#define LIS3DH_PARAM_CLK (SPI_CLK_5MHZ)
118
123#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17)
124#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7)
125#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16)
127
132#define MULLE_NVRAM_SPI_DEV SPI_DEV(0)
133#define MULLE_NVRAM_SPI_CLK SPI_CLK_5MHZ
134#define MULLE_NVRAM_SPI_CS SPI_HWCS(3)
135#define MULLE_NVRAM_CAPACITY 512
136#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1
138
143#define MULLE_NOR_SPI_DEV SPI_DEV(0)
144#define MULLE_NOR_SPI_CLK SPI_CLK_5MHZ
145#define MULLE_NOR_SPI_CS SPI_HWCS(2)
151#define MTD_0 mtd_dev_get(0)
153
158#define MULLE_VBAT_ADC_LINE ADC_LINE(6)
159#define MULLE_VCHR_ADC_LINE ADC_LINE(7)
NVRAM offsets for the Eistec Mulle IoT board.