Register definition for the MMA8x5x accelerometer driver. More...

Detailed Description

Register definition for the MMA8x5x accelerometer driver.

Author: Johann Fischer j.fis.nosp@m.cher.nosp@m.@phyt.nosp@m.ec.d.nosp@m.e; Hauke Petersen

Register addresses
#define	MMA8X5X_STATUS 0x00
	Data or FIFO Status.

#define	MMA8X5X_OUT_X_MSB 0x01
	[7:0] are 8 MSBs of X data

#define	MMA8X5X_OUT_X_LSB 0x02
	[7:4] are 4 LSBs of X data

#define	MMA8X5X_OUT_Y_MSB 0x03
	[7:0] are 8 MSBs of Y data

#define	MMA8X5X_OUT_Y_LSB 0x04
	[7:4] are 4 LSBs of Y data

#define	MMA8X5X_OUT_Z_MSB 0x05
	[7:0] are 8 MSBs of Z data

#define	MMA8X5X_OUT_Z_LSB 0x06
	[7:4] are 8 LSBs of Z data

#define	MMA8X5X_F_SETUP 0x09
	FIFO setup.

#define	MMA8X5X_TRIG_CFG 0x0A
	Map of FIFO data capture events.

#define	MMA8X5X_SYSMOD 0x0B
	Current System mode.

#define	MMA8X5X_INT_SOURCE 0x0C
	Interrupt status.

#define	MMA8X5X_WHO_AM_I 0x0D
	Device ID.

#define	MMA8X5X_XYZ_DATA_CFG 0x0E
	Dynamic Range Settings.

#define	MMA8X5X_HP_FILTER_CUTOFF 0x0F
	High-Pass Filter Selection.

#define	MMA8X5X_PL_STATUS 0x10
	Landscape/Portrait orientation status.

#define	MMA8X5X_PL_CFG 0x11
	Landscape/Portrait configuration.

#define	MMA8X5X_PL_COUNT 0x12
	Landscape/Portrait debounce counter.

#define	MMA8X5X_PL_BF_ZCOMP 0x13
	Back/Front, Z-Lock Trip threshold.

#define	MMA8X5X_P_L_THS_REG 0x14
	Portrait/Landscape Threshold and Hysteresis.

#define	MMA8X5X_FF_MT_CFG 0x15
	Freefall/Motion functional block configuration.

#define	MMA8X5X_FF_MT_SRC 0x16
	Freefall/Motion event source register.

#define	MMA8X5X_FF_MT_THS 0x17
	Freefall/Motion threshold register.

#define	MMA8X5X_FF_MT_COUNT 0x18
	Freefall/Motion debounce counter.

#define	MMA8X5X_TRANSIENT_CFG 0x1D
	Transient functional block configuration.

#define	MMA8X5X_TRANSIENT_SRC 0x1E
	Transient event status register.

#define	MMA8X5X_TRANSIENT_THS 0x1F
	Transient event threshold.

#define	MMA8X5X_TRANSIENT_COUNT 0x20
	Transient debounce counter.

#define	MMA8X5X_PULSE_CFG 0x21
	Pulse enable configuration.

#define	MMA8X5X_PULSE_SRC 0x22
	Pulse detection source.

#define	MMA8X5X_PULSE_THSX 0x23
	X pulse threshold.

#define	MMA8X5X_PULSE_THSY 0x24
	Y pulse threshold.

#define	MMA8X5X_PULSE_THSZ 0x25
	Z pulse threshold.

#define	MMA8X5X_PULSE_TMLT 0x26
	Time limit for pulse.

#define	MMA8X5X_PULSE_LTCY 0x27
	Latency time for 2nd pulse.

#define	MMA8X5X_PULSE_WIND 0x28
	Window time for 2nd pulse.

#define	MMA8X5X_ASLP_COUNT 0x29
	Counter setting for Auto-SLEEP.

#define	MMA8X5X_CTRL_REG1 0x2A
	Data rates and modes setting.

#define	MMA8X5X_CTRL_REG2 0x2B
	Sleep Enable, OS modes, RST, ST.

#define	MMA8X5X_CTRL_REG3 0x2C
	Wake from Sleep, IPOL, PP_OD.

#define	MMA8X5X_CTRL_REG4 0x2D
	Interrupt enable register.

#define	MMA8X5X_CTRL_REG5 0x2E
	Interrupt pin (INT1/INT2) map.

#define	MMA8X5X_OFF_X 0x2F
	X-axis offset adjust.

#define	MMA8X5X_OFF_Y 0x30
	Y-axis offset adjust.

#define	MMA8X5X_OFF_Z 0x31
	Z-axis offset adjust.

#define	MMA8X5X_STATUS_XDR (1 << 0)
	MMA8x5x register bitfields.

#define	MMA8X5X_STATUS_YDR (1 << 1)

#define	MMA8X5X_STATUS_ZDR (1 << 2)

#define	MMA8X5X_STATUS_ZYXDR (1 << 3)

#define	MMA8X5X_STATUS_XOW (1 << 4)

#define	MMA8X5X_STATUS_YOW (1 << 5)

#define	MMA8X5X_STATUS_ZOW (1 << 6)

#define	MMA8X5X_STATUS_ZYXOW (1 << 7)

#define	MMA8X5X_F_STATUS_F_CNT_MASK 0x3F

#define	MMA8X5X_F_STATUS_F_WMRK_FLAG (1 << 6)

#define	MMA8X5X_F_STATUS_F_OVF (1 << 7)

#define	MMA8X5X_F_SETUP_MODE_MASK 0xC0

#define	MMA8X5X_F_SETUP_MODE_DISABLED 0

#define	MMA8X5X_F_SETUP_MODE_CIRCULAR 1

#define	MMA8X5X_F_SETUP_MODE_STOP 2

#define	MMA8X5X_F_SETUP_MODE_TRIGGER 3

#define	MMA8X5X_F_SETUP_F_WMRK_MASK 0x3F

#define	MMA8X5X_TRIG_CFG_FF_MT (1 << 2)

#define	MMA8X5X_TRIG_CFG_PULSE (1 << 3)

#define	MMA8X5X_TRIG_CFG_LNDPRT (1 << 4)

#define	MMA8X5X_TRIG_CFG_TRANS (1 << 5)

#define	MMA8X5X_SYSMOD_MASK 0x3

#define	MMA8X5X_SYSMOD_STANDBY 0

#define	MMA8X5X_SYSMOD_WAKE 1

#define	MMA8X5X_SYSMOD_SLEEP 2

#define	MMA8X5X_SYSMOD_FGT_MASK 0x7C

#define	MMA8X5X_SYSMOD_FGERR (1 << 7)

#define	MMA8X5X_INT_SOURCE_DRDY (1 << 0)

#define	MMA8X5X_INT_SOURCE_FF_MT (1 << 2)

#define	MMA8X5X_INT_SOURCE_PULSE (1 << 3)

#define	MMA8X5X_INT_SOURCE_LNDPRT (1 << 4)

#define	MMA8X5X_INT_SOURCE_TRANS (1 << 5)

#define	MMA8X5X_INT_SOURCE_FIFO (1 << 6)

#define	MMA8X5X_INT_SOURCE_ASLP (1 << 7)

#define	MMA8X5X_XYZ_DATA_CFG_FS_MASK 0x3

#define	MMA8X5X_XYZ_DATA_CFG_HPF_OUT (1 << 4)

#define	MMA8X5X_HP_FILTER_SEL_MASK 0x03

#define	MMA8X5X_HP_FILTER_LPF_EN (1 << 4)

#define	MMA8X5X_HP_FILTER_HPF_BYP (1 << 5)

#define	MMA8X5X_PL_STATUS_BAFRO (1 << 0)

#define	MMA8X5X_PL_STATUS_LAPO_MASK 0x6

#define	MMA8X5X_PL_STATUS_LAPO_P_UP 0

#define	MMA8X5X_PL_STATUS_LAPO_P_DOWN 1

#define	MMA8X5X_PL_STATUS_LAPO_L_RIGHT 2

#define	MMA8X5X_PL_STATUS_LAPO_L_LEFT 3

#define	MMA8X5X_PL_STATUS_LO (1 << 6)

#define	MMA8X5X_PL_STATUS_NEWLP (1 << 7)

#define	MMA8X5X_PL_CFG_PL_EN (1 << 6)

#define	MMA8X5X_PL_CFG_DBCNTM (1 << 7)

#define	MMA8X5X_PL_BF_ZCOMP_ZLOCK_MASK 0x07

#define	MMA8X5X_PL_BF_ZCOMP_BKFR_MASK 0xC0

#define	MMA8X5X_P_L_HYS_MASK 0x07

#define	MMA8X5X_P_L_THS_MASK 0xF8

#define	MMA8X5X_FF_MT_CFG_XEFE (1 << 3)

#define	MMA8X5X_FF_MT_CFG_YEFE (1 << 4)

#define	MMA8X5X_FF_MT_CFG_ZEFE (1 << 5)

#define	MMA8X5X_FF_MT_CFG_OAE (1 << 6)

#define	MMA8X5X_FF_MT_CFG_ELE (1 << 7)

#define	MMA8X5X_FF_MT_SRC_XHP (1 << 0)

#define	MMA8X5X_FF_MT_SRC_XHE (1 << 1)

#define	MMA8X5X_FF_MT_SRC_YHP (1 << 2)

#define	MMA8X5X_FF_MT_SRC_YHE (1 << 3)

#define	MMA8X5X_FF_MT_SRC_ZHP (1 << 4)

#define	MMA8X5X_FF_MT_SRC_ZHE (1 << 5)

#define	MMA8X5X_FF_MT_SRC_EA (1 << 7)

#define	MMA8X5X_FF_MT_THS_MASK 0x7F

#define	MMA8X5X_FF_MT_THS_DBCNTM (1 << 7)

#define	MMA8X5X_TRANSIENT_CFG_HPF_BYP (1 << 0)

#define	MMA8X5X_TRANSIENT_CFG_XTEFE (1 << 1)

#define	MMA8X5X_TRANSIENT_CFG_YTEFE (1 << 2)

#define	MMA8X5X_TRANSIENT_CFG_ZTEFE (1 << 3)

#define	MMA8X5X_TRANSIENT_CFG_ELE (1 << 4)

#define	MMA8X5X_TRANSIENT_SRC_XTPOL (1 << 0)

#define	MMA8X5X_TRANSIENT_SRC_XTEVENT (1 << 1)

#define	MMA8X5X_TRANSIENT_SRC_YTPOL (1 << 2)

#define	MMA8X5X_TRANSIENT_SRC_YTEVENT (1 << 3)

#define	MMA8X5X_TRANSIENT_SRC_ZTPOL (1 << 4)

#define	MMA8X5X_TRANSIENT_SRC_ZTEVENT (1 << 5)

#define	MMA8X5X_TRANSIENT_SRC_EA (1 << 6)

#define	MMA8X5X_TRANSIENT_THS_MASK 0x7F

#define	MMA8X5X_TRANSIENT_THS_DBCNTM (1<< 7)

#define	MMA8X5X_PULSE_CFG_XSPEFE (1 << 0)

#define	MMA8X5X_PULSE_CFG_XDPEFE (1 << 1)

#define	MMA8X5X_PULSE_CFG_YSPEFE (1 << 2)

#define	MMA8X5X_PULSE_CFG_YDPEFE (1 << 3)

#define	MMA8X5X_PULSE_CFG_ZSPEFE (1 << 4)

#define	MMA8X5X_PULSE_CFG_ZDPEFE (1 << 5)

#define	MMA8X5X_PULSE_CFG_ELE (1 << 6)

#define	MMA8X5X_PULSE_CFG_DPA (1 << 7)

#define	MMA8X5X_PULSE_SRC_POLX (1 << 0)

#define	MMA8X5X_PULSE_SRC_POLY (1 << 1)

#define	MMA8X5X_PULSE_SRC_POLZ (1 << 2)

#define	MMA8X5X_PULSE_SRC_DPE (1 << 3)

#define	MMA8X5X_PULSE_SRC_AXX (1 << 4)

#define	MMA8X5X_PULSE_SRC_AXY (1 << 5)

#define	MMA8X5X_PULSE_SRC_AXZ (1 << 6)

#define	MMA8X5X_PULSE_SRC_EA (1 << 7)

#define	MMA8X5X_PULSE_THSX_MASK 0x7F

#define	MMA8X5X_PULSE_THSY_MASK 0x7F

#define	MMA8X5X_PULSE_THSZ_MASK 0x7F

#define	MMA8X5X_CTRL_REG1_ACTIVE (1 << 0)

#define	MMA8X5X_CTRL_REG1_F_READ (1 << 1)

#define	MMA8X5X_CTRL_REG1_DR_MASK 0x38

#define	MMA8X5X_CTRL_REG1_DR_SHIFT 3

#define	MMA8X5X_CTRL_REG1_DR(x)

#define	MMA8X5X_CTRL_REG1_ASR_MASK 0xC0

#define	MMA8X5X_CTRL_REG1_ASR_50HZ 0

#define	MMA8X5X_CTRL_REG1_ASR_12HZ5 1

#define	MMA8X5X_CTRL_REG1_ASR_6HZ25 2

#define	MMA8X5X_CTRL_REG1_ASR_1HZ56 3

#define	MMA8X5X_CTRL_REG2_MODS_MASK 0x3

#define	MMA8X5X_CTRL_REG2_MODS_NORMAL 0

#define	MMA8X5X_CTRL_REG2_MODS_LNLP 1

#define	MMA8X5X_CTRL_REG2_MODS_HR 2

#define	MMA8X5X_CTRL_REG2_MODS_LP 3

#define	MMA8X5X_CTRL_REG2_SLPE (1 << 2)

#define	MMA8X5X_CTRL_REG2_SMODS_MASK 0x18

#define	MMA8X5X_CTRL_REG2_SMODS_NORMAL 0

#define	MMA8X5X_CTRL_REG2_SMODS_LNLP 1

#define	MMA8X5X_CTRL_REG2_SMODS_HR 2

#define	MMA8X5X_CTRL_REG2_SMODS_LP 3

#define	MMA8X5X_CTRL_REG2_RST (1 << 6)

#define	MMA8X5X_CTRL_REG2_ST (1 << 7)

#define	MMA8X5X_CTRL_REG3_PP_OD (1 << 0)

#define	MMA8X5X_CTRL_REG3_IPOL (1 << 1)

#define	MMA8X5X_CTRL_REG3_WAKE_FF_MT (1 << 3)

#define	MMA8X5X_CTRL_REG3_WAKE_PULSE (1 << 4)

#define	MMA8X5X_CTRL_REG3_WAKE_LNDPRT (1 << 5)

#define	MMA8X5X_CTRL_REG3_WAKE_TRANS (1 << 6)

#define	MMA8X5X_CTRL_REG3_FIFO_GATE (1 << 7)

#define	MMA8X5X_CTRL_REG4_INT_EN_DRDY (1 << 0)

#define	MMA8X5X_CTRL_REG4_INT_EN_FF_MT (1 << 2)

#define	MMA8X5X_CTRL_REG4_INT_EN_PULSE (1 << 3)

#define	MMA8X5X_CTRL_REG4_INT_EN_LNDPRT (1 << 4)

#define	MMA8X5X_CTRL_REG4_INT_EN_TRANS (1 << 5)

#define	MMA8X5X_CTRL_REG4_INT_EN_FIFO (1 << 6)

#define	MMA8X5X_CTRL_REG4_INT_EN_ASLP (1 << 7)

#define	MMA8X5X_CTRL_REG5_INT_CFG_DRDY (1 << 0)

#define	MMA8X5X_CTRL_REG5_INT_CFG_FF_MT (1 << 2)

#define	MMA8X5X_CTRL_REG5_INT_CFG_PULSE (1 << 3)

#define	MMA8X5X_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)

#define	MMA8X5X_CTRL_REG5_INT_CFG_TRANS (1 << 5)

#define	MMA8X5X_CTRL_REG5_INT_CFG_FIFO (1 << 6)

#define	MMA8X5X_CTRL_REG5_INT_CFG_ASLP (1 << 7)

Macro Definition Documentation

◆ MMA8X5X_ASLP_COUNT

#define MMA8X5X_ASLP_COUNT 0x29

Counter setting for Auto-SLEEP.

Definition at line 70 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1

#define MMA8X5X_CTRL_REG1 0x2A

Data rates and modes setting.

Definition at line 71 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ACTIVE

#define MMA8X5X_CTRL_REG1_ACTIVE (1 << 0)

Definition at line 206 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ASR_12HZ5

#define MMA8X5X_CTRL_REG1_ASR_12HZ5 1

Definition at line 214 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ASR_1HZ56

#define MMA8X5X_CTRL_REG1_ASR_1HZ56 3

Definition at line 216 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ASR_50HZ

#define MMA8X5X_CTRL_REG1_ASR_50HZ 0

Definition at line 213 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ASR_6HZ25

#define MMA8X5X_CTRL_REG1_ASR_6HZ25 2

Definition at line 215 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_ASR_MASK

#define MMA8X5X_CTRL_REG1_ASR_MASK 0xC0

Definition at line 212 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_DR

#define MMA8X5X_CTRL_REG1_DR ( x )

Value:

(((uint8_t)(((uint8_t)(x))<<MMA8X5X_CTRL_REG1_DR_SHIFT))\

&MMA8X5X_CTRL_REG1_DR_MASK)

Definition at line 210 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_DR_MASK

#define MMA8X5X_CTRL_REG1_DR_MASK 0x38

Definition at line 208 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_DR_SHIFT

#define MMA8X5X_CTRL_REG1_DR_SHIFT 3

Definition at line 209 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG1_F_READ

#define MMA8X5X_CTRL_REG1_F_READ (1 << 1)

Definition at line 207 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2

#define MMA8X5X_CTRL_REG2 0x2B

Sleep Enable, OS modes, RST, ST.

Definition at line 72 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_MODS_HR

#define MMA8X5X_CTRL_REG2_MODS_HR 2

Definition at line 221 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_MODS_LNLP

#define MMA8X5X_CTRL_REG2_MODS_LNLP 1

Definition at line 220 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_MODS_LP

#define MMA8X5X_CTRL_REG2_MODS_LP 3

Definition at line 222 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_MODS_MASK

#define MMA8X5X_CTRL_REG2_MODS_MASK 0x3

Definition at line 218 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_MODS_NORMAL

#define MMA8X5X_CTRL_REG2_MODS_NORMAL 0

Definition at line 219 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_RST

#define MMA8X5X_CTRL_REG2_RST (1 << 6)

Definition at line 229 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SLPE

#define MMA8X5X_CTRL_REG2_SLPE (1 << 2)

Definition at line 223 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SMODS_HR

#define MMA8X5X_CTRL_REG2_SMODS_HR 2

Definition at line 227 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SMODS_LNLP

#define MMA8X5X_CTRL_REG2_SMODS_LNLP 1

Definition at line 226 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SMODS_LP

#define MMA8X5X_CTRL_REG2_SMODS_LP 3

Definition at line 228 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SMODS_MASK

#define MMA8X5X_CTRL_REG2_SMODS_MASK 0x18

Definition at line 224 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_SMODS_NORMAL

#define MMA8X5X_CTRL_REG2_SMODS_NORMAL 0

Definition at line 225 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG2_ST

#define MMA8X5X_CTRL_REG2_ST (1 << 7)

Definition at line 230 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3

#define MMA8X5X_CTRL_REG3 0x2C

Wake from Sleep, IPOL, PP_OD.

Definition at line 73 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_FIFO_GATE

#define MMA8X5X_CTRL_REG3_FIFO_GATE (1 << 7)

Definition at line 238 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_IPOL

#define MMA8X5X_CTRL_REG3_IPOL (1 << 1)

Definition at line 233 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_PP_OD

#define MMA8X5X_CTRL_REG3_PP_OD (1 << 0)

Definition at line 232 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_WAKE_FF_MT

#define MMA8X5X_CTRL_REG3_WAKE_FF_MT (1 << 3)

Definition at line 234 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_WAKE_LNDPRT

#define MMA8X5X_CTRL_REG3_WAKE_LNDPRT (1 << 5)

Definition at line 236 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_WAKE_PULSE

#define MMA8X5X_CTRL_REG3_WAKE_PULSE (1 << 4)

Definition at line 235 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG3_WAKE_TRANS

#define MMA8X5X_CTRL_REG3_WAKE_TRANS (1 << 6)

Definition at line 237 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4

#define MMA8X5X_CTRL_REG4 0x2D

Interrupt enable register.

Definition at line 74 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_ASLP

#define MMA8X5X_CTRL_REG4_INT_EN_ASLP (1 << 7)

Definition at line 246 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_DRDY

#define MMA8X5X_CTRL_REG4_INT_EN_DRDY (1 << 0)

Definition at line 240 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_FF_MT

#define MMA8X5X_CTRL_REG4_INT_EN_FF_MT (1 << 2)

Definition at line 241 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_FIFO

#define MMA8X5X_CTRL_REG4_INT_EN_FIFO (1 << 6)

Definition at line 245 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_LNDPRT

#define MMA8X5X_CTRL_REG4_INT_EN_LNDPRT (1 << 4)

Definition at line 243 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_PULSE

#define MMA8X5X_CTRL_REG4_INT_EN_PULSE (1 << 3)

Definition at line 242 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG4_INT_EN_TRANS

#define MMA8X5X_CTRL_REG4_INT_EN_TRANS (1 << 5)

Definition at line 244 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5

#define MMA8X5X_CTRL_REG5 0x2E

Interrupt pin (INT1/INT2) map.

Definition at line 75 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_ASLP

#define MMA8X5X_CTRL_REG5_INT_CFG_ASLP (1 << 7)

Definition at line 254 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_DRDY

#define MMA8X5X_CTRL_REG5_INT_CFG_DRDY (1 << 0)

Definition at line 248 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_FF_MT

#define MMA8X5X_CTRL_REG5_INT_CFG_FF_MT (1 << 2)

Definition at line 249 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_FIFO

#define MMA8X5X_CTRL_REG5_INT_CFG_FIFO (1 << 6)

Definition at line 253 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_LNDPRT

#define MMA8X5X_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)

Definition at line 251 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_PULSE

#define MMA8X5X_CTRL_REG5_INT_CFG_PULSE (1 << 3)

Definition at line 250 of file mma8x5x_regs.h.

◆ MMA8X5X_CTRL_REG5_INT_CFG_TRANS

#define MMA8X5X_CTRL_REG5_INT_CFG_TRANS (1 << 5)

Definition at line 252 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP

#define MMA8X5X_F_SETUP 0x09

FIFO setup.

Definition at line 42 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_F_WMRK_MASK

#define MMA8X5X_F_SETUP_F_WMRK_MASK 0x3F

Definition at line 103 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_MODE_CIRCULAR

#define MMA8X5X_F_SETUP_MODE_CIRCULAR 1

Definition at line 100 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_MODE_DISABLED

#define MMA8X5X_F_SETUP_MODE_DISABLED 0

Definition at line 99 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_MODE_MASK

#define MMA8X5X_F_SETUP_MODE_MASK 0xC0

Definition at line 98 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_MODE_STOP

#define MMA8X5X_F_SETUP_MODE_STOP 2

Definition at line 101 of file mma8x5x_regs.h.

◆ MMA8X5X_F_SETUP_MODE_TRIGGER

#define MMA8X5X_F_SETUP_MODE_TRIGGER 3

Definition at line 102 of file mma8x5x_regs.h.

◆ MMA8X5X_F_STATUS_F_CNT_MASK

#define MMA8X5X_F_STATUS_F_CNT_MASK 0x3F

Definition at line 94 of file mma8x5x_regs.h.

◆ MMA8X5X_F_STATUS_F_OVF

#define MMA8X5X_F_STATUS_F_OVF (1 << 7)

Definition at line 96 of file mma8x5x_regs.h.

◆ MMA8X5X_F_STATUS_F_WMRK_FLAG

#define MMA8X5X_F_STATUS_F_WMRK_FLAG (1 << 6)

Definition at line 95 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG

#define MMA8X5X_FF_MT_CFG 0x15

Freefall/Motion functional block configuration.

Definition at line 54 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG_ELE

#define MMA8X5X_FF_MT_CFG_ELE (1 << 7)

Definition at line 154 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG_OAE

#define MMA8X5X_FF_MT_CFG_OAE (1 << 6)

Definition at line 153 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG_XEFE

#define MMA8X5X_FF_MT_CFG_XEFE (1 << 3)

Definition at line 150 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG_YEFE

#define MMA8X5X_FF_MT_CFG_YEFE (1 << 4)

Definition at line 151 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_CFG_ZEFE

#define MMA8X5X_FF_MT_CFG_ZEFE (1 << 5)

Definition at line 152 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_COUNT

#define MMA8X5X_FF_MT_COUNT 0x18

Freefall/Motion debounce counter.

Definition at line 57 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC

#define MMA8X5X_FF_MT_SRC 0x16

Freefall/Motion event source register.

Definition at line 55 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_EA

#define MMA8X5X_FF_MT_SRC_EA (1 << 7)

Definition at line 162 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_XHE

#define MMA8X5X_FF_MT_SRC_XHE (1 << 1)

Definition at line 157 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_XHP

#define MMA8X5X_FF_MT_SRC_XHP (1 << 0)

Definition at line 156 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_YHE

#define MMA8X5X_FF_MT_SRC_YHE (1 << 3)

Definition at line 159 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_YHP

#define MMA8X5X_FF_MT_SRC_YHP (1 << 2)

Definition at line 158 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_ZHE

#define MMA8X5X_FF_MT_SRC_ZHE (1 << 5)

Definition at line 161 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_SRC_ZHP

#define MMA8X5X_FF_MT_SRC_ZHP (1 << 4)

Definition at line 160 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_THS

#define MMA8X5X_FF_MT_THS 0x17

Freefall/Motion threshold register.

Definition at line 56 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_THS_DBCNTM

#define MMA8X5X_FF_MT_THS_DBCNTM (1 << 7)

Definition at line 165 of file mma8x5x_regs.h.

◆ MMA8X5X_FF_MT_THS_MASK

#define MMA8X5X_FF_MT_THS_MASK 0x7F

Definition at line 164 of file mma8x5x_regs.h.

◆ MMA8X5X_HP_FILTER_CUTOFF

#define MMA8X5X_HP_FILTER_CUTOFF 0x0F

High-Pass Filter Selection.

Definition at line 48 of file mma8x5x_regs.h.

◆ MMA8X5X_HP_FILTER_HPF_BYP

#define MMA8X5X_HP_FILTER_HPF_BYP (1 << 5)

Definition at line 130 of file mma8x5x_regs.h.

◆ MMA8X5X_HP_FILTER_LPF_EN

#define MMA8X5X_HP_FILTER_LPF_EN (1 << 4)

Definition at line 129 of file mma8x5x_regs.h.

◆ MMA8X5X_HP_FILTER_SEL_MASK

#define MMA8X5X_HP_FILTER_SEL_MASK 0x03

Definition at line 128 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE

#define MMA8X5X_INT_SOURCE 0x0C

Interrupt status.

Definition at line 45 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_ASLP

#define MMA8X5X_INT_SOURCE_ASLP (1 << 7)

Definition at line 123 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_DRDY

#define MMA8X5X_INT_SOURCE_DRDY (1 << 0)

Definition at line 117 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_FF_MT

#define MMA8X5X_INT_SOURCE_FF_MT (1 << 2)

Definition at line 118 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_FIFO

#define MMA8X5X_INT_SOURCE_FIFO (1 << 6)

Definition at line 122 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_LNDPRT

#define MMA8X5X_INT_SOURCE_LNDPRT (1 << 4)

Definition at line 120 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_PULSE

#define MMA8X5X_INT_SOURCE_PULSE (1 << 3)

Definition at line 119 of file mma8x5x_regs.h.

◆ MMA8X5X_INT_SOURCE_TRANS

#define MMA8X5X_INT_SOURCE_TRANS (1 << 5)

Definition at line 121 of file mma8x5x_regs.h.

◆ MMA8X5X_OFF_X

#define MMA8X5X_OFF_X 0x2F

X-axis offset adjust.

Definition at line 76 of file mma8x5x_regs.h.

◆ MMA8X5X_OFF_Y

#define MMA8X5X_OFF_Y 0x30

Y-axis offset adjust.

Definition at line 77 of file mma8x5x_regs.h.

◆ MMA8X5X_OFF_Z

#define MMA8X5X_OFF_Z 0x31

Z-axis offset adjust.

Definition at line 78 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_X_LSB

#define MMA8X5X_OUT_X_LSB 0x02

[7:4] are 4 LSBs of X data

Definition at line 37 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_X_MSB

#define MMA8X5X_OUT_X_MSB 0x01

[7:0] are 8 MSBs of X data

Definition at line 36 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_Y_LSB

#define MMA8X5X_OUT_Y_LSB 0x04

[7:4] are 4 LSBs of Y data

Definition at line 39 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_Y_MSB

#define MMA8X5X_OUT_Y_MSB 0x03

[7:0] are 8 MSBs of Y data

Definition at line 38 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_Z_LSB

#define MMA8X5X_OUT_Z_LSB 0x06

[7:4] are 8 LSBs of Z data

Definition at line 41 of file mma8x5x_regs.h.

◆ MMA8X5X_OUT_Z_MSB

#define MMA8X5X_OUT_Z_MSB 0x05

[7:0] are 8 MSBs of Z data

Definition at line 40 of file mma8x5x_regs.h.

◆ MMA8X5X_P_L_HYS_MASK

#define MMA8X5X_P_L_HYS_MASK 0x07

Definition at line 147 of file mma8x5x_regs.h.

◆ MMA8X5X_P_L_THS_MASK

#define MMA8X5X_P_L_THS_MASK 0xF8

Definition at line 148 of file mma8x5x_regs.h.

◆ MMA8X5X_P_L_THS_REG

#define MMA8X5X_P_L_THS_REG 0x14

Portrait/Landscape Threshold and Hysteresis.

Definition at line 53 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_BF_ZCOMP

#define MMA8X5X_PL_BF_ZCOMP 0x13

Back/Front, Z-Lock Trip threshold.

Definition at line 52 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_BF_ZCOMP_BKFR_MASK

#define MMA8X5X_PL_BF_ZCOMP_BKFR_MASK 0xC0

Definition at line 145 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_BF_ZCOMP_ZLOCK_MASK

#define MMA8X5X_PL_BF_ZCOMP_ZLOCK_MASK 0x07

Definition at line 144 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_CFG

#define MMA8X5X_PL_CFG 0x11

Landscape/Portrait configuration.

Definition at line 50 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_CFG_DBCNTM

#define MMA8X5X_PL_CFG_DBCNTM (1 << 7)

Definition at line 142 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_CFG_PL_EN

#define MMA8X5X_PL_CFG_PL_EN (1 << 6)

Definition at line 141 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_COUNT

#define MMA8X5X_PL_COUNT 0x12

Landscape/Portrait debounce counter.

Definition at line 51 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS

#define MMA8X5X_PL_STATUS 0x10

Landscape/Portrait orientation status.

Definition at line 49 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_BAFRO

#define MMA8X5X_PL_STATUS_BAFRO (1 << 0)

Definition at line 132 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LAPO_L_LEFT

#define MMA8X5X_PL_STATUS_LAPO_L_LEFT 3

Definition at line 137 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LAPO_L_RIGHT

#define MMA8X5X_PL_STATUS_LAPO_L_RIGHT 2

Definition at line 136 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LAPO_MASK

#define MMA8X5X_PL_STATUS_LAPO_MASK 0x6

Definition at line 133 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LAPO_P_DOWN

#define MMA8X5X_PL_STATUS_LAPO_P_DOWN 1

Definition at line 135 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LAPO_P_UP

#define MMA8X5X_PL_STATUS_LAPO_P_UP 0

Definition at line 134 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_LO

#define MMA8X5X_PL_STATUS_LO (1 << 6)

Definition at line 138 of file mma8x5x_regs.h.

◆ MMA8X5X_PL_STATUS_NEWLP

#define MMA8X5X_PL_STATUS_NEWLP (1 << 7)

Definition at line 139 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG

#define MMA8X5X_PULSE_CFG 0x21

Pulse enable configuration.

Definition at line 62 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_DPA

#define MMA8X5X_PULSE_CFG_DPA (1 << 7)

Definition at line 191 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_ELE

#define MMA8X5X_PULSE_CFG_ELE (1 << 6)

Definition at line 190 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_XDPEFE

#define MMA8X5X_PULSE_CFG_XDPEFE (1 << 1)

Definition at line 185 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_XSPEFE

#define MMA8X5X_PULSE_CFG_XSPEFE (1 << 0)

Definition at line 184 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_YDPEFE

#define MMA8X5X_PULSE_CFG_YDPEFE (1 << 3)

Definition at line 187 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_YSPEFE

#define MMA8X5X_PULSE_CFG_YSPEFE (1 << 2)

Definition at line 186 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_ZDPEFE

#define MMA8X5X_PULSE_CFG_ZDPEFE (1 << 5)

Definition at line 189 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_CFG_ZSPEFE

#define MMA8X5X_PULSE_CFG_ZSPEFE (1 << 4)

Definition at line 188 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_LTCY

#define MMA8X5X_PULSE_LTCY 0x27

Latency time for 2nd pulse.

Definition at line 68 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC

#define MMA8X5X_PULSE_SRC 0x22

Pulse detection source.

Definition at line 63 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_AXX

#define MMA8X5X_PULSE_SRC_AXX (1 << 4)

Definition at line 197 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_AXY

#define MMA8X5X_PULSE_SRC_AXY (1 << 5)

Definition at line 198 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_AXZ

#define MMA8X5X_PULSE_SRC_AXZ (1 << 6)

Definition at line 199 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_DPE

#define MMA8X5X_PULSE_SRC_DPE (1 << 3)

Definition at line 196 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_EA

#define MMA8X5X_PULSE_SRC_EA (1 << 7)

Definition at line 200 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_POLX

#define MMA8X5X_PULSE_SRC_POLX (1 << 0)

Definition at line 193 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_POLY

#define MMA8X5X_PULSE_SRC_POLY (1 << 1)

Definition at line 194 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_SRC_POLZ

#define MMA8X5X_PULSE_SRC_POLZ (1 << 2)

Definition at line 195 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSX

#define MMA8X5X_PULSE_THSX 0x23

X pulse threshold.

Definition at line 64 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSX_MASK

#define MMA8X5X_PULSE_THSX_MASK 0x7F

Definition at line 202 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSY

#define MMA8X5X_PULSE_THSY 0x24

Y pulse threshold.

Definition at line 65 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSY_MASK

#define MMA8X5X_PULSE_THSY_MASK 0x7F

Definition at line 203 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSZ

#define MMA8X5X_PULSE_THSZ 0x25

Z pulse threshold.

Definition at line 66 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_THSZ_MASK

#define MMA8X5X_PULSE_THSZ_MASK 0x7F

Definition at line 204 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_TMLT

#define MMA8X5X_PULSE_TMLT 0x26

Time limit for pulse.

Definition at line 67 of file mma8x5x_regs.h.

◆ MMA8X5X_PULSE_WIND

#define MMA8X5X_PULSE_WIND 0x28

Window time for 2nd pulse.

Definition at line 69 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS

#define MMA8X5X_STATUS 0x00

Data or FIFO Status.

Definition at line 35 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_XDR

#define MMA8X5X_STATUS_XDR (1 << 0)

MMA8x5x register bitfields.

Definition at line 85 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_XOW

#define MMA8X5X_STATUS_XOW (1 << 4)

Definition at line 89 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_YDR

#define MMA8X5X_STATUS_YDR (1 << 1)

Definition at line 86 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_YOW

#define MMA8X5X_STATUS_YOW (1 << 5)

Definition at line 90 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_ZDR

#define MMA8X5X_STATUS_ZDR (1 << 2)

Definition at line 87 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_ZOW

#define MMA8X5X_STATUS_ZOW (1 << 6)

Definition at line 91 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_ZYXDR

#define MMA8X5X_STATUS_ZYXDR (1 << 3)

Definition at line 88 of file mma8x5x_regs.h.

◆ MMA8X5X_STATUS_ZYXOW

#define MMA8X5X_STATUS_ZYXOW (1 << 7)

Definition at line 92 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD

#define MMA8X5X_SYSMOD 0x0B

Current System mode.

Definition at line 44 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_FGERR

#define MMA8X5X_SYSMOD_FGERR (1 << 7)

Definition at line 115 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_FGT_MASK

#define MMA8X5X_SYSMOD_FGT_MASK 0x7C

Definition at line 114 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_MASK

#define MMA8X5X_SYSMOD_MASK 0x3

Definition at line 110 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_SLEEP

#define MMA8X5X_SYSMOD_SLEEP 2

Definition at line 113 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_STANDBY

#define MMA8X5X_SYSMOD_STANDBY 0

Definition at line 111 of file mma8x5x_regs.h.

◆ MMA8X5X_SYSMOD_WAKE

#define MMA8X5X_SYSMOD_WAKE 1

Definition at line 112 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG

#define MMA8X5X_TRANSIENT_CFG 0x1D

Transient functional block configuration.

Definition at line 58 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG_ELE

#define MMA8X5X_TRANSIENT_CFG_ELE (1 << 4)

Definition at line 171 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG_HPF_BYP

#define MMA8X5X_TRANSIENT_CFG_HPF_BYP (1 << 0)

Definition at line 167 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG_XTEFE

#define MMA8X5X_TRANSIENT_CFG_XTEFE (1 << 1)

Definition at line 168 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG_YTEFE

#define MMA8X5X_TRANSIENT_CFG_YTEFE (1 << 2)

Definition at line 169 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_CFG_ZTEFE

#define MMA8X5X_TRANSIENT_CFG_ZTEFE (1 << 3)

Definition at line 170 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_COUNT

#define MMA8X5X_TRANSIENT_COUNT 0x20

Transient debounce counter.

Definition at line 61 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC

#define MMA8X5X_TRANSIENT_SRC 0x1E

Transient event status register.

Definition at line 59 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_EA

#define MMA8X5X_TRANSIENT_SRC_EA (1 << 6)

Definition at line 179 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_XTEVENT

#define MMA8X5X_TRANSIENT_SRC_XTEVENT (1 << 1)

Definition at line 174 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_XTPOL

#define MMA8X5X_TRANSIENT_SRC_XTPOL (1 << 0)

Definition at line 173 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_YTEVENT

#define MMA8X5X_TRANSIENT_SRC_YTEVENT (1 << 3)

Definition at line 176 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_YTPOL

#define MMA8X5X_TRANSIENT_SRC_YTPOL (1 << 2)

Definition at line 175 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_ZTEVENT

#define MMA8X5X_TRANSIENT_SRC_ZTEVENT (1 << 5)

Definition at line 178 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_SRC_ZTPOL

#define MMA8X5X_TRANSIENT_SRC_ZTPOL (1 << 4)

Definition at line 177 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_THS

#define MMA8X5X_TRANSIENT_THS 0x1F

Transient event threshold.

Definition at line 60 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_THS_DBCNTM

#define MMA8X5X_TRANSIENT_THS_DBCNTM (1<< 7)

Definition at line 182 of file mma8x5x_regs.h.

◆ MMA8X5X_TRANSIENT_THS_MASK

#define MMA8X5X_TRANSIENT_THS_MASK 0x7F

Definition at line 181 of file mma8x5x_regs.h.

◆ MMA8X5X_TRIG_CFG

#define MMA8X5X_TRIG_CFG 0x0A

Map of FIFO data capture events.

Definition at line 43 of file mma8x5x_regs.h.

◆ MMA8X5X_TRIG_CFG_FF_MT

#define MMA8X5X_TRIG_CFG_FF_MT (1 << 2)

Definition at line 105 of file mma8x5x_regs.h.

◆ MMA8X5X_TRIG_CFG_LNDPRT

#define MMA8X5X_TRIG_CFG_LNDPRT (1 << 4)

Definition at line 107 of file mma8x5x_regs.h.

◆ MMA8X5X_TRIG_CFG_PULSE

#define MMA8X5X_TRIG_CFG_PULSE (1 << 3)

Definition at line 106 of file mma8x5x_regs.h.

◆ MMA8X5X_TRIG_CFG_TRANS

#define MMA8X5X_TRIG_CFG_TRANS (1 << 5)

Definition at line 108 of file mma8x5x_regs.h.

◆ MMA8X5X_WHO_AM_I

#define MMA8X5X_WHO_AM_I 0x0D

Device ID.

Definition at line 46 of file mma8x5x_regs.h.

◆ MMA8X5X_XYZ_DATA_CFG

#define MMA8X5X_XYZ_DATA_CFG 0x0E

Dynamic Range Settings.

Definition at line 47 of file mma8x5x_regs.h.

◆ MMA8X5X_XYZ_DATA_CFG_FS_MASK

#define MMA8X5X_XYZ_DATA_CFG_FS_MASK 0x3

Definition at line 125 of file mma8x5x_regs.h.

◆ MMA8X5X_XYZ_DATA_CFG_HPF_OUT

#define MMA8X5X_XYZ_DATA_CFG_HPF_OUT (1 << 4)

Definition at line 126 of file mma8x5x_regs.h.