39#if IS_ACTIVE(CONFIG_EFM32_XTIMER_USE_LETIMER)
40#define XTIMER_DEV (TIMER_DEV(1))
41#define XTIMER_HZ (32768UL)
42#define XTIMER_WIDTH (16)
44#define XTIMER_DEV (TIMER_DEV(0))
45#define XTIMER_HZ (250000UL)
46#define XTIMER_WIDTH (16)
48#define XTIMER_CHAN (0)
55#define PB0_PIN GPIO_PIN(PD, 15)
56#define PB1_PIN GPIO_PIN(PD, 13)
57#define PB2_PIN GPIO_PIN(PB, 11)
64#define LED0_PIN GPIO_PIN(PF, 2)
65#define LED1_PIN GPIO_PIN(PF, 3)
74#define CORETEMP_ADC ADC_LINE(0)
81#define LED0_ON gpio_set(LED0_PIN)
82#define LED0_OFF gpio_clear(LED0_PIN)
83#define LED0_TOGGLE gpio_toggle(LED0_PIN)
84#define LED1_ON gpio_set(LED1_PIN)
85#define LED1_OFF gpio_clear(LED1_PIN)
86#define LED1_TOGGLE gpio_toggle(LED1_PIN)
Native CPU peripheral configuration.
Low-level GPIO peripheral driver interface definitions.
Low-level SPI peripheral driver interface definition.