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cfg_clock_default.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2017 Freie Universität Berlin
3 * 2019 Inria
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
22#define CLK_L4L5WX_CFG_CLOCK_DEFAULT_H
23
24#include "cfg_clock_common_lx_u5_wx.h"
25#include "kernel_defines.h"
26#include "macros/units.h"
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
36#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
37#error "HSE clock frequency must be between 4MHz and 48MHz"
38#endif
39
40/* The following parameters configure a 80MHz system clock with PLL as input clock */
41#ifndef CONFIG_CLOCK_PLL_SRC_MSI
42#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
43 IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
44#define CONFIG_CLOCK_PLL_SRC_MSI 0
45#else
46#define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
47#endif
48#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
49#ifndef CONFIG_CLOCK_PLL_SRC_HSE
50#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
51 !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
52#define CONFIG_CLOCK_PLL_SRC_HSE 1
53#else
54#define CONFIG_CLOCK_PLL_SRC_HSE 0
55#endif
56#endif
57#ifndef CONFIG_CLOCK_PLL_SRC_HSI
58#define CONFIG_CLOCK_PLL_SRC_HSI 0
59#endif
60#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
61#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
62#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
63#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
64#else /* CONFIG_CLOCK_PLL_SRC_ */
65#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
66#endif
67#ifndef CONFIG_CLOCK_PLL_M
68#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
69#define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
70#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
71#define CONFIG_CLOCK_PLL_M (1) /* HSE at 8MHz */
72#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
73#define CONFIG_CLOCK_PLL_M (4) /* HSE at 32MHz */
74#else
75#define CONFIG_CLOCK_PLL_M (2) /* HSI at 16MHz */
76#endif
77#endif
78#ifndef CONFIG_CLOCK_PLL_N
79#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(32))
80/* For STM32WL, VCO output frequency ((PLL input clock frequency / PLLM ) x PLLN )
81 must be between 96 and 344 MHz. PLLN can have values <=127 & >=6 */
82#if IS_ACTIVE(CPU_FAM_STM32WL)
83#define CONFIG_CLOCK_PLL_N (12)
84#else
85#define CONFIG_CLOCK_PLL_N (16)
86#endif /* CPU_FAM_STM32WL */
87#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
88 (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CONFIG_CLOCK_HSE == MHZ(16)))
89#define CONFIG_CLOCK_PLL_N (32)
90#else
91#if defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
92 defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
93 defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
94 defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
95 defined(CPU_LINE_STM32L4S9xx)
96#define CONFIG_CLOCK_PLL_N (30)
97#elif defined(CPU_FAM_STM32L5)
98#define CONFIG_CLOCK_PLL_N (27)
99#else
100#define CONFIG_CLOCK_PLL_N (20)
101#endif
102#endif
103#endif
104#ifndef CONFIG_CLOCK_PLL_Q
105#define CONFIG_CLOCK_PLL_Q (2)
106#endif
107#ifndef CONFIG_CLOCK_PLL_R
108#define CONFIG_CLOCK_PLL_R (2)
109#endif
110
111#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
112#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
113
114#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
115#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
116
117#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
118#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
119
120#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
121/* PLL configuration: make sure your values are legit!
122 *
123 * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
124 * with:
125 * PLL_IN: input clock, HSE or MSI
126 * M: pre-divider, allowed range: [1:8]
127 * N: multiplier, allowed range: [8:86]
128 * R: post-divider, allowed range: [2:8]
129 *
130 * Also the following constraints need to be met:
131 * (PLL_IN / M) -> [4MHz:16MHz]
132 * (PLL_IN / M) * N -> [64MHz:344MHz]
133 * CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
134 */
135#define CLOCK_CORECLOCK \
136 ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
137
138/* Set max allowed sysclk */
139#if defined(CPU_FAM_STM32WL)
140#define CLOCK_CORECLOCK_MAX MHZ(48)
141#elif defined(CPU_FAM_STM32WB)
142#define CLOCK_CORECLOCK_MAX MHZ(64)
143#elif defined(CPU_FAM_STM32L5)
144#define CLOCK_CORECLOCK_MAX MHZ(110)
145#elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
146 defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
147 defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
148 defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
149 defined(CPU_LINE_STM32L4S9xx)
150#define CLOCK_CORECLOCK_MAX MHZ(120)
151#else /* all the other L4 */
152#define CLOCK_CORECLOCK_MAX MHZ(80)
153#endif
154
155#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
156#if CLOCK_CORECLOCK_MAX == MHZ(48)
157#error "SYSCLK cannot exceed 48MHz"
158#elif CLOCK_CORECLOCK_MAX == MHZ(64)
159#error "SYSCLK cannot exceed 64MHz"
160#elif CLOCK_CORECLOCK_MAX == MHZ(80)
161#error "SYSCLK cannot exceed 80MHz"
162#elif CLOCK_CORECLOCK_MAX == MHZ(110)
163#error "SYSCLK cannot exceed 110MHz"
164#elif CLOCK_CORECLOCK_MAX == MHZ(120)
165#error "SYSCLK cannot exceed 120MHz"
166#else
167#error "invalid SYSCLK"
168#endif
169#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
170#endif /* CONFIG_USE_CLOCK_PLL */
171
172#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 48/64/80/120MHz */
173
174#ifndef CONFIG_CLOCK_APB1_DIV
175#define CONFIG_CLOCK_APB1_DIV (4)
176#endif
177#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 48/64/80/120MHz */
178#ifndef CONFIG_CLOCK_APB2_DIV
179#define CONFIG_CLOCK_APB2_DIV (2)
180#endif
181#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 48/64/80/120MHz */
184#ifdef __cplusplus
185}
186#endif
187
188#endif /* CLK_L4L5WX_CFG_CLOCK_DEFAULT_H */
cfg_clock_common_lx_u5_wx.h
Base STM32Lx/U5/Wx clock configuration.
kernel_defines.h
Common macros and compiler attributes/pragmas configuration.
units.h
Unit helper macros.