cc2538_gpio.h

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/*
 * SPDX-FileCopyrightText: 2014 Loci Controls Inc.
 * SPDX-License-Identifier: LGPL-2.1-only
 */
 
#pragma once

 
#include <stdint.h>
 
#include "cc2538.h"
 
#ifdef __cplusplus
extern "C" {
#endif

enum {
    PORT_A = 0,
    PORT_B = 1,
    PORT_C = 2,
    PORT_D = 3,
};
 
#define GPIO_PORT_SHIFT 3                              
#define GPIO_BITS_PER_PORT ( 1 << GPIO_PORT_SHIFT )    
#define GPIO_BIT_MASK      ( GPIO_BITS_PER_PORT - 1 )  

#define PIN_MASK(n) ( 1 << (n) )

#define GPIO_NUM_TO_PORT_NUM(gpio_num) ( (gpio_num) >> GPIO_PORT_SHIFT )

#define GPIO_BIT_NUM(gpio_num) ( (gpio_num) & GPIO_BIT_MASK )

#define GPIO_PXX_TO_NUM(port_num, bit_num) ( ((port_num) << GPIO_PORT_SHIFT) | (bit_num) )

#define GPIO_NUM_TO_DEV(gpio_num) ( GPIO_A + GPIO_NUM_TO_PORT_NUM(gpio_num) )

#define gpio_hardware_control(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->AFSEL |= PIN_MASK(GPIO_BIT_NUM(gpio_num)) )

#define gpio_software_control(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->AFSEL &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )

#define gpio_dir_output(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DIR |= PIN_MASK(GPIO_BIT_NUM(gpio_num)) )

#define gpio_dir_input(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DIR &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )

#define cc2538_gpio_read(gpio_num) ( (GPIO_NUM_TO_DEV(gpio_num)->DATA >> GPIO_BIT_NUM(gpio_num)) & 1 )

#define cc2538_gpio_clear(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DATA &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )

enum {
    GPIO_PA0 = GPIO_PXX_TO_NUM(PORT_A, 0),          
    GPIO_PA1 = GPIO_PXX_TO_NUM(PORT_A, 1),          
    GPIO_PA2 = GPIO_PXX_TO_NUM(PORT_A, 2),          
    GPIO_PA3 = GPIO_PXX_TO_NUM(PORT_A, 3),          
    GPIO_PA4 = GPIO_PXX_TO_NUM(PORT_A, 4),          
    GPIO_PA5 = GPIO_PXX_TO_NUM(PORT_A, 5),          
    GPIO_PA6 = GPIO_PXX_TO_NUM(PORT_A, 6),          
    GPIO_PA7 = GPIO_PXX_TO_NUM(PORT_A, 7),          
    GPIO_PB0 = GPIO_PXX_TO_NUM(PORT_B, 0),          
    GPIO_PB1 = GPIO_PXX_TO_NUM(PORT_B, 1),          
    GPIO_PB2 = GPIO_PXX_TO_NUM(PORT_B, 2),          
    GPIO_PB3 = GPIO_PXX_TO_NUM(PORT_B, 3),          
    GPIO_PB4 = GPIO_PXX_TO_NUM(PORT_B, 4),          
    GPIO_PB5 = GPIO_PXX_TO_NUM(PORT_B, 5),          
    GPIO_PB6 = GPIO_PXX_TO_NUM(PORT_B, 6),          
    GPIO_PB7 = GPIO_PXX_TO_NUM(PORT_B, 7),          
    GPIO_PC0 = GPIO_PXX_TO_NUM(PORT_C, 0),          
    GPIO_PC1 = GPIO_PXX_TO_NUM(PORT_C, 1),          
    GPIO_PC2 = GPIO_PXX_TO_NUM(PORT_C, 2),          
    GPIO_PC3 = GPIO_PXX_TO_NUM(PORT_C, 3),          
    GPIO_PC4 = GPIO_PXX_TO_NUM(PORT_C, 4),          
    GPIO_PC5 = GPIO_PXX_TO_NUM(PORT_C, 5),          
    GPIO_PC6 = GPIO_PXX_TO_NUM(PORT_C, 6),          
    GPIO_PC7 = GPIO_PXX_TO_NUM(PORT_C, 7),          
    GPIO_PD0 = GPIO_PXX_TO_NUM(PORT_D, 0),          
    GPIO_PD1 = GPIO_PXX_TO_NUM(PORT_D, 1),          
    GPIO_PD2 = GPIO_PXX_TO_NUM(PORT_D, 2),          
    GPIO_PD3 = GPIO_PXX_TO_NUM(PORT_D, 3),          
    GPIO_PD4 = GPIO_PXX_TO_NUM(PORT_D, 4),          
    GPIO_PD5 = GPIO_PXX_TO_NUM(PORT_D, 5),          
    GPIO_PD6 = GPIO_PXX_TO_NUM(PORT_D, 6),          
    GPIO_PD7 = GPIO_PXX_TO_NUM(PORT_D, 7),          
};

typedef struct {
    cc2538_reg_t RESERVED1[255];                    
    cc2538_reg_t DATA;                              
    cc2538_reg_t DIR;                               
    cc2538_reg_t IS;                                
    cc2538_reg_t IBE;                               
    cc2538_reg_t IEV;                               
    cc2538_reg_t IE;                                
    cc2538_reg_t RIS;                               
    cc2538_reg_t MIS;                               
    cc2538_reg_t IC;                                
    cc2538_reg_t AFSEL;                             
    cc2538_reg_t RESERVED2[63];                     
    cc2538_reg_t GPIOLOCK;                          
    cc2538_reg_t GPIOCR;                            
    cc2538_reg_t RESERVED3[118];                    
    cc2538_reg_t PMUX;                              
    cc2538_reg_t P_EDGE_CTRL;                       
    cc2538_reg_t RESERVED4[2];                      
    cc2538_reg_t PI_IEN;                            
    cc2538_reg_t RESERVED5[1];                      
    cc2538_reg_t IRQ_DETECT_ACK;                    
    cc2538_reg_t USB_IRQ_ACK;                       
    cc2538_reg_t IRQ_DETECT_UNMASK;                 
    cc2538_reg_t RESERVED6[567];                    
} cc2538_gpio_t;

#define GPIO_BASE           (0x400d9000)

#define GPIO_PORTNUM_SHIFT  (12U)           
#define GPIO_PORTNUM_MASK   (0x00007000)    
#define GPIO_PIN_MASK       (0x00000007)    
#define GPIO_PORT_MASK      (0xfffff000)    

#define GPIO_A ((cc2538_gpio_t *)0x400d9000)    
#define GPIO_B ((cc2538_gpio_t *)0x400da000)    
#define GPIO_C ((cc2538_gpio_t *)0x400db000)    
#define GPIO_D ((cc2538_gpio_t *)0x400dc000)    

 typedef struct {
     cc2538_reg_t SEL[32];      
     cc2538_reg_t OVER[32];     
     cc2538_reg_t PINS[21];     
 } cc2538_ioc_t;

 typedef enum {
     UART0_TXD = 0,      
     UART1_RTS,          
     UART1_TXD,          
     SSI0_TXD,           
     SSI0_CLK_OUT,       
     SSI0_FSS_OUT,       
     SSI0_TX_SER,        
     SSI1_TXD,           
     SSI1_CLK_OUT,       
     SSI1_FSS_OUT,       
     SSI1_TX_SER,        
     I2C_SDA_OUT,        
     I2C_SCL_OUT,        
     GPT0_ICP1,          
     GPT0_ICP2,          
     GPT1_ICP1,          
     GPT1_ICP2,          
     GPT2_ICP1,          
     GPT2_ICP2,          
     GPT3_ICP1,          
     GPT3_ICP2 ,         
 } cc2538_ioc_sel_t;


 typedef enum {
     UART0_RXD = 0,      
     UART1_CTS,          
     UART1_RXD,          
     SSI0_CLK,           
     SSI0_RXD,           
     SSI0_FSS_IN,        
     SSI0_CLK_IN,        
     SSI1_CLK,           
     SSI1_RXD,           
     SSI1_FSS_IN,        
     SSI1_CLK_IN,        
     I2C_SDA_IN,         
     I2C_SCL_IN,         
     GPT0_OCP1,          
     GPT0_OCP2,          
     GPT1_OCP1,          
     GPT1_OCP2,          
     GPT2_OCP1,          
     GPT2_OCP2,          
     GPT3_OCP1,          
     GPT3_OCP2,          
 } cc2538_ioc_pin_t;


 typedef enum {
     OVERRIDE_DISABLE    = 0x0,
     OVERRIDE_ANALOG     = 0x1,
     OVERRIDE_PULLDOWN   = 0x2,
     OVERRIDE_PULLUP     = 0x4,
     OVERRIDE_ENABLE     = 0x8,
 } cc2538_ioc_over_t;

#define IOC_OVERRIDE_OE   0x00000008    
#define IOC_OVERRIDE_PUE  0x00000004    
#define IOC_OVERRIDE_PDE  0x00000002    
#define IOC_OVERRIDE_ANA  0x00000001    
#define IOC_OVERRIDE_DIS  0x00000000    

#define IOC    ((cc2538_ioc_t *)0x400d4000)

#define IOC_PXX_OVER    (IOC->OVER)
#define IOC_PXX_SEL     (IOC->SEL)
 
#ifdef __cplusplus
} /* end extern "C" */
#endif