The friendly Operating System for the Internet of Things
Default interrupt vectors shared by Cortex-M based CPUs. More...
Definition in file vectors_cortexm.h.
|Use this macro to make interrupt functions overridable with the dummy_handler as fallback in case they are not implemented. |
|Put this macro in front of the array holding the interrupt vectors. |
|Number of Cortex-M non-ISR exceptions. More...|
|This function is the default entry point after a system reset. More...|
|Non-maskable interrupt handler. More...|
|Hard fault exception handler. More...|
|Default handler used as weak alias for not implemented ISR vectors. More...|
|#define CPU_NONISR_EXCEPTIONS (15)|
Per default, all interrupt handlers are mapped to the dummy handler using a weak symbol. This means the handlers can be (should be) overwritten in the RIOT code by just implementing a function with the name of the targeted interrupt routine.
Hard faults are triggered on errors during exception processing. Typical causes of hard faults are access to un-aligned pointers on Cortex-M0 CPUs and calls of function pointers that are set to NULL.
Non-maskable interrupts have the highest priority other than the reset event and can not be masked (surprise surprise...). They can be triggered by software and some peripherals. So far, they are not used in RIOT.
After a system reset, the following steps are necessary and carried out: