cc2538_ssi_t Struct Reference

SSI component registers. More...

Detailed Description

Definition at line 31 of file cc2538_ssi.h.

#include </tmp/RIOT/cpu/cc2538/include/cc2538_ssi.h>

Data Fields

union {
   cc2538_reg_t   CR0
 SSI Control Register 0.
 
   struct {
      cc2538_reg_t   DSS: 4
 SSI data size select.
 
      cc2538_reg_t   FRF: 2
 SSI frame format select.
 
      cc2538_reg_t   SPO: 1
 SSI serial clock polarity.
 
      cc2538_reg_t   SPH: 1
 SSI serial clock phase.
 
      cc2538_reg_t   SCR: 8
 SSI serial clock rate.
 
      cc2538_reg_t   RESERVED: 16
 Reserved bits.
 
   }   CR0bits
 
}; 
 
union {
   cc2538_reg_t   CR1
 SSI Control Register 1.
 
   struct {
      cc2538_reg_t   LBM: 1
 SSI loop-back mode.
 
      cc2538_reg_t   SSE: 1
 SSI synchronous serial port enable.
 
      cc2538_reg_t   MS: 1
 SSI master and slave select.
 
      cc2538_reg_t   SOD: 1
 SSI slave mode output disable.
 
      cc2538_reg_t   RESERVED: 28
 Reserved bits.
 
   }   CR1bits
 
}; 
 
cc2538_reg_t DR
 SSI Data register.
 
union {
   cc2538_reg_t   SR
 SSI FIFO/busy Status Register.
 
   struct {
      cc2538_reg_t   TFE: 1
 SSI transmit FIFO empty.
 
      cc2538_reg_t   TNF: 1
 SSI transmit FIFO not full.
 
      cc2538_reg_t   RNE: 1
 SSI receive FIFO not empty.
 
      cc2538_reg_t   RFF: 1
 SSI receive FIFO full.
 
      cc2538_reg_t   BSY: 1
 SSI busy bit.
 
      cc2538_reg_t   RESERVED: 27
 Reserved bits.
 
   }   SRbits
 
}; 
 
cc2538_reg_t CPSR
 SSI Clock Register.
 
cc2538_reg_t IM
 SSI Interrupt Mask register.
 
cc2538_reg_t RIS
 SSI Raw Interrupt Status register.
 
cc2538_reg_t MIS
 SSI Masked Interrupt Status register.
 
cc2538_reg_t ICR
 SSI Interrupt Clear Register.
 
cc2538_reg_t DMACTL
 SSI uDMA Control Register. More...
 
cc2538_reg_t CC
 SSI clock configuration.
 

Field Documentation

◆ DMACTL

cc2538_reg_t cc2538_ssi_t::DMACTL

Definition at line 73 of file cc2538_ssi.h.


The documentation for this struct was generated from the following file: