stm32f4/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include "periph_cpu_common.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 #define CPUID_ADDR (0x1fff7a10)
32 
36 enum {
37  PORT_A = 0,
38  PORT_B = 1,
39  PORT_C = 2,
40  PORT_D = 3,
41  PORT_E = 4,
42  PORT_F = 5,
43  PORT_G = 6,
44  PORT_H = 7,
45  PORT_I = 8
46 };
47 
51 #if defined(CPU_MODEL_STM32F401RE) || defined(CPU_MODEL_STM32F410RB) || defined(CPU_MODEL_STM32F411RE)|| defined(CPU_MODEL_STM32F413ZH)
52 #define ADC_DEVS (1U)
53 #elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG) || defined(CPU_MODEL_STM32F446RE) || defined(CPU_MODEL_STM32F429ZI)
54 #define ADC_DEVS (3U)
55 #endif
56 
57 #ifndef DOXYGEN
58 
62 #define HAVE_ADC_RES_T
63 typedef enum {
64  ADC_RES_6BIT = 0x03000000,
65  ADC_RES_8BIT = 0x02000000,
66  ADC_RES_10BIT = 0x01000000,
67  ADC_RES_12BIT = 0x00000000,
68  ADC_RES_14BIT = 1,
69  ADC_RES_16BIT = 2
70 } adc_res_t;
72 #endif /* ndef DOXYGEN */
73 
77 typedef struct {
78  gpio_t pin;
79  uint8_t dev;
80  uint8_t chan;
81 } adc_conf_t;
82 
88 static inline void dma_poweron(int stream)
89 {
90  if (stream < 8) {
91  periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
92  }
93  else {
94  periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
95  }
96 }
97 
107 static inline DMA_TypeDef *dma_base(int stream)
108 {
109  return (stream < 8) ? DMA1 : DMA2;
110 }
111 
119 static inline DMA_Stream_TypeDef *dma_stream(int stream)
120 {
121  uint32_t base = (uint32_t)dma_base(stream);
122 
123  return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
124 }
125 
133 static inline int dma_hl(int stream)
134 {
135  return ((stream & 0x4) >> 2);
136 }
137 
143 static inline uint32_t dma_ifc(int stream)
144 {
145  switch (stream & 0x3) {
146  case 0:
147  return (1 << 5);
148  case 1:
149  return (1 << 11);
150  case 2:
151  return (1 << 21);
152  case 3:
153  return (1 << 27);
154  default:
155  return 0;
156  }
157 }
158 
159 static inline void dma_isr_enable(int stream)
160 {
161  if (stream < 7) {
162  NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
163  }
164  else if (stream == 7) {
165  NVIC_EnableIRQ(DMA1_Stream7_IRQn);
166  }
167  else if (stream < 13) {
168  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
169  }
170  else if (stream < 16) {
171  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
172  }
173 }
174 
175 #ifdef __cplusplus
176 }
177 #endif
178 
179 #endif /* PERIPH_CPU_H */
180 
ADC resolution: 12 bit.
static int dma_hl(int stream)
Select high or low DMA interrupt register based on stream number.
static void dma_isr_enable(int stream)
Enable DMA interrupts.
enum IRQn IRQn_Type
Interrupt Number Definition.
static uint32_t dma_ifc(int stream)
Get the interrupt flag clear bit position in the DMA LIFCR register.
static void dma_poweron(int stream)
Power on the DMA device the given stream belongs to.
static DMA_TypeDef * dma_base(int stream)
Get DMA base register.
not supported by hardware
ADC resolution: 10 bit.
gpio_t adc_conf_t
ADC configuration wrapper.
not supported by hardware
not supported by hardware
not supported by hardware
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
static DMA_Stream_TypeDef * dma_stream(int stream)
Get the DMA stream base address.