stm32f2/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Engineering-Spirit
3  * Copyright (C) 2016 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include "periph_cpu_common.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 enum {
34  PORT_A = 0,
35  PORT_B = 1,
36  PORT_C = 2,
37  PORT_D = 3,
38  PORT_E = 4,
39  PORT_F = 5,
40  PORT_G = 6,
41  PORT_H = 7,
42  PORT_I = 8
43 };
44 
48 #define ADC_DEVS (2U)
49 
53 typedef struct {
54  gpio_t pin;
55  uint8_t dev;
56  uint8_t chan;
57 } adc_conf_t;
58 
63 #define HAVE_ADC_RES_T
64 typedef enum {
65  ADC_RES_6BIT = 0x03000000,
66  ADC_RES_8BIT = 0x02000000,
67  ADC_RES_10BIT = 0x01000000,
68  ADC_RES_12BIT = 0x00000000,
71 } adc_res_t;
77 typedef struct {
78  gpio_t pin;
79  uint8_t chan;
80 } dac_conf_t;
81 
87 static inline void dma_poweron(int stream)
88 {
89  if (stream < 8) {
90  periph_clk_en(AHB1, RCC_AHB1ENR_DMA1EN);
91  } else {
92  periph_clk_en(AHB1, RCC_AHB1ENR_DMA2EN);
93  }
94 }
95 
105 static inline DMA_TypeDef *dma_base(int stream)
106 {
107  return (stream < 8) ? DMA1 : DMA2;
108 }
109 
117 static inline DMA_Stream_TypeDef *dma_stream(int stream)
118 {
119  uint32_t base = (uint32_t)dma_base(stream);
120  return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
121 }
122 
130 static inline int dma_hl(int stream)
131 {
132  return ((stream & 0x4) >> 2);
133 }
134 
140 static inline uint32_t dma_ifc(int stream)
141 {
142  switch (stream & 0x3) {
143  case 0: /* 0 and 4 */
144  return (1 << 5);
145  case 1: /* 1 and 5 */
146  return (1 << 11);
147  case 2: /* 2 and 6 */
148  return (1 << 21);
149  case 3: /* 3 and 7 */
150  return (1 << 27);
151  default:
152  return 0;
153  }
154 }
155 
161 static inline void dma_isr_enable(int stream)
162 {
163  if (stream < 7) {
164  NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
165  }
166  else if (stream == 7) {
167  NVIC_EnableIRQ(DMA1_Stream7_IRQn);
168  }
169  else if (stream < 13) {
170  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
171  }
172  else if (stream < 16) {
173  NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
174  }
175 }
176 
177 #ifdef __cplusplus
178 }
179 #endif
180 
181 #endif /* PERIPH_CPU_H */
182 
ADC resolution: 12 bit.
static void dma_isr_enable(int stream)
Enable DMA interrupts.
static uint32_t dma_ifc(int stream)
Get the interrupt flag clear bit position in the DMA LIFCR register.
enum IRQn IRQn_Type
Interrupt Number Definition.
static DMA_TypeDef * dma_base(int stream)
Get DMA base register.
ADC resolution: 14 bit (not supported)
ADC resolution: 10 bit.
static void dma_poweron(int stream)
Power on the DMA device the given stream belongs to.
ADC resolution: 16 bit (not supported)
ADC resolution: 8 bit.
ADC resolution: 6 bit.
static DMA_Stream_TypeDef * dma_stream(int stream)
Get the DMA stream base address.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
CPU specific DAC configuration.
static int dma_hl(int stream)
Select high or low DMA interrupt register based on stream number.
CPU specific ADC configuration.