stm32_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
37  defined(CPU_FAM_STM32L1)
38 #define CLOCK_LSI (37000U)
39 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
40  defined(CPU_FAM_STM32L4)
41 #define CLOCK_LSI (32000U)
42 #else
43 #error "error: LSI clock speed not defined for your target CPU"
44 #endif
45 
49 extern uint32_t _cpuid_address;
53 #define CPUID_ADDR (&_cpuid_address)
54 
57 #define CPUID_LEN (12U)
58 
62 #define TIMER_CHAN (4U)
63 
68 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
69 #define PERIPH_SPI_NEEDS_TRANSFER_REG
70 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
71 
76 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) \
77  || defined(CPU_FAM_STM32F4) || defined(DOXYGEN)
78 #define PM_NUM_MODES (2U)
79 #endif
80 
84 typedef enum {
85  APB1,
86  APB2,
87 #if defined(CPU_FAM_STM32L0)
88  AHB,
89  IOP,
90 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
91  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
92  AHB,
93 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
94  || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
95  AHB1,
96  AHB2,
97  AHB3
98 #else
99 #warning "unsupported stm32XX family"
100 #endif
101 } bus_t;
102 
103 #ifndef DOXYGEN
104 
108 #define HAVE_GPIO_T
109 typedef uint32_t gpio_t;
111 #endif
112 
116 #define GPIO_UNDEF (0xffffffff)
117 
121 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
122 
129 #define SPI_HWCS_MASK (0xffffff00)
130 
137 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
138 
142 typedef enum {
143 #ifdef CPU_FAM_STM32F1
144  GPIO_AF_OUT_PP = 0xb,
145  GPIO_AF_OUT_OD = 0xf,
146 #else
147  GPIO_AF0 = 0,
155 #ifndef CPU_FAM_STM32F0
164 #endif
165 #endif
166 } gpio_af_t;
167 
168 #ifndef CPU_FAM_STM32F1
169 
177 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
178 
179 #ifndef DOXYGEN
180 
184 #define HAVE_GPIO_MODE_T
185 typedef enum {
186  GPIO_IN = GPIO_MODE(0, 0, 0),
187  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
188  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
189  GPIO_OUT = GPIO_MODE(1, 0, 0),
190  GPIO_OD = GPIO_MODE(1, 0, 1),
191  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
192 } gpio_mode_t;
199 #define HAVE_GPIO_FLANK_T
200 typedef enum {
201  GPIO_RISING = 1,
202  GPIO_FALLING = 2,
203  GPIO_BOTH = 3
204 } gpio_flank_t;
206 #endif /* ndef DOXYGEN */
207 #endif /* ndef CPU_FAM_STM32F1 */
208 
212 typedef struct {
213  gpio_t pin;
214  uint8_t chan;
215 } dac_conf_t;
216 
220 typedef struct {
221  TIM_TypeDef *dev;
222  uint32_t max;
223  uint32_t rcc_mask;
224  uint8_t bus;
225  uint8_t irqn;
226 } timer_conf_t;
227 
231 typedef struct {
232  gpio_t pin;
233  uint8_t cc_chan;
234 } pwm_chan_t;
235 
239 typedef struct {
240  TIM_TypeDef *dev;
241  uint32_t rcc_mask;
244  gpio_af_t af;
245  uint8_t bus;
246 } pwm_conf_t;
247 
251 typedef struct {
252  USART_TypeDef *dev;
253  uint32_t rcc_mask;
254  gpio_t rx_pin;
255  gpio_t tx_pin;
256 #ifndef CPU_FAM_STM32F1
257  gpio_af_t rx_af;
258  gpio_af_t tx_af;
259 #endif
260  uint8_t bus;
261  uint8_t irqn;
262 #if 0 /* TODO */
263  uint8_t dma_stream;
264  uint8_t dma_chan;
265 #endif
266 #ifdef UART_USE_HW_FC
267  gpio_t cts_pin;
268  gpio_t rts_pin;
269 #ifndef CPU_FAM_STM32F1
270  gpio_af_t cts_af;
271  gpio_af_t rts_af;
272 #endif
273 #endif
274 } uart_conf_t;
275 
279 typedef struct {
280  SPI_TypeDef *dev;
281  gpio_t mosi_pin;
282  gpio_t miso_pin;
283  gpio_t sclk_pin;
284  gpio_t cs_pin;
285 #ifndef CPU_FAM_STM32F1
286  gpio_af_t af;
287 #endif
288  uint32_t rccmask;
289  uint8_t apbbus;
290 } spi_conf_t;
291 
299 uint32_t periph_apb_clk(uint8_t bus);
300 
307 void periph_clk_en(bus_t bus, uint32_t mask);
308 
315 void periph_clk_dis(bus_t bus, uint32_t mask);
316 
323 void gpio_init_af(gpio_t pin, gpio_af_t af);
324 
330 void gpio_init_analog(gpio_t pin);
331 
332 #ifdef __cplusplus
333 }
334 #endif
335 
336 #endif /* PERIPH_CPU_COMMON_H */
337 
use alternate function 4
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
use alternate function 7
emit interrupt on rising flank
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
use alternate function 8
use alternate function 10
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
gpio_t pin
pin connected to the line
use alternate function 6
use alternate function 14
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
use alternate function 3
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
use alternate function 1
PWM configuration structure.
gpio_af_t af
pin alternate function
emit interrupt on both flanks
use alternate function 0
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
use alternate function 5
static DMA_Stream_TypeDef * dma_stream(int stream)
Get the DMA stream base address.
use alternate function 11
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
gpio_af_t rx_af
alternate function for RX pin
input, no pull
TIM_TypeDef * dev
timer device
DAC line configuration data.
uint32_t rccmask
bit in the RCC peripheral enable register
uint32_t _cpuid_address
CPU specific LSI clock speed.
not supported
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI module configuration options.
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
input, pull-down
gpio_af_t af
alternate function used
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
use alternate function 2
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.