stm32_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
37  defined(CPU_FAM_STM32L1)
38 #define CLOCK_LSI (37000U)
39 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
40  defined(CPU_FAM_STM32L4)
41 #define CLOCK_LSI (32000U)
42 #else
43 #error "error: LSI clock speed not defined for your target CPU"
44 #endif
45 
51 #define CPUID_LEN (12U)
52 
56 #define PROVIDES_PM_LAYERED_OFF
57 
61 #define TIMER_CHAN (4U)
62 
67 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
68 #define PERIPH_SPI_NEEDS_TRANSFER_REG
69 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
70 
75 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) \
76  || defined(CPU_FAM_STM32F4) || defined(DOXYGEN)
77 #define PM_NUM_MODES (2U)
78 #endif
79 
83 typedef enum {
84  APB1,
85  APB2,
86 #if defined(CPU_FAM_STM32L0)
87  AHB,
88  IOP,
89 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
90  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
91  AHB,
92 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
93  || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
94  AHB1,
95  AHB2,
96  AHB3
97 #else
98 #warning "unsupported stm32XX family"
99 #endif
100 } bus_t;
101 
102 #ifndef DOXYGEN
103 
107 #define HAVE_GPIO_T
108 typedef uint32_t gpio_t;
110 #endif
111 
115 #define GPIO_UNDEF (0xffffffff)
116 
120 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
121 
128 #define SPI_HWCS_MASK (0xffffff00)
129 
136 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
137 
141 typedef enum {
142 #ifdef CPU_FAM_STM32F1
143  GPIO_AF_OUT_PP = 0xb,
144  GPIO_AF_OUT_OD = 0xf,
145 #else
146  GPIO_AF0 = 0,
154 #ifndef CPU_FAM_STM32F0
163 #endif
164 #endif
165 } gpio_af_t;
166 
167 #ifndef CPU_FAM_STM32F1
168 
176 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
177 
178 #ifndef DOXYGEN
179 
183 #define HAVE_GPIO_MODE_T
184 typedef enum {
185  GPIO_IN = GPIO_MODE(0, 0, 0),
186  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
187  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
188  GPIO_OUT = GPIO_MODE(1, 0, 0),
189  GPIO_OD = GPIO_MODE(1, 0, 1),
190  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
191 } gpio_mode_t;
198 #define HAVE_GPIO_FLANK_T
199 typedef enum {
200  GPIO_RISING = 1,
201  GPIO_FALLING = 2,
202  GPIO_BOTH = 3
203 } gpio_flank_t;
205 #endif /* ndef DOXYGEN */
206 #endif /* ndef CPU_FAM_STM32F1 */
207 
211 typedef struct {
212  gpio_t pin;
213  uint8_t chan;
214 } dac_conf_t;
215 
219 typedef struct {
220  TIM_TypeDef *dev;
221  uint32_t max;
222  uint32_t rcc_mask;
223  uint8_t bus;
224  uint8_t irqn;
225 } timer_conf_t;
226 
230 typedef struct {
231  gpio_t pin;
232  uint8_t cc_chan;
233 } pwm_chan_t;
234 
238 typedef struct {
239  TIM_TypeDef *dev;
240  uint32_t rcc_mask;
243  gpio_af_t af;
244  uint8_t bus;
245 } pwm_conf_t;
246 
250 typedef struct {
251  USART_TypeDef *dev;
252  uint32_t rcc_mask;
253  gpio_t rx_pin;
254  gpio_t tx_pin;
255 #ifndef CPU_FAM_STM32F1
256  gpio_af_t rx_af;
257  gpio_af_t tx_af;
258 #endif
259  uint8_t bus;
260  uint8_t irqn;
261 #if 0 /* TODO */
262  uint8_t dma_stream;
263  uint8_t dma_chan;
264 #endif
265 #ifdef MODULE_STM32_PERIPH_UART_HW_FC
266  gpio_t cts_pin;
267  gpio_t rts_pin;
268 #ifndef CPU_FAM_STM32F1
269  gpio_af_t cts_af;
270  gpio_af_t rts_af;
271 #endif
272 #endif
273 } uart_conf_t;
274 
278 typedef struct {
279  SPI_TypeDef *dev;
280  gpio_t mosi_pin;
281  gpio_t miso_pin;
282  gpio_t sclk_pin;
283  gpio_t cs_pin;
284 #ifndef CPU_FAM_STM32F1
285  gpio_af_t af;
286 #endif
287  uint32_t rccmask;
288  uint8_t apbbus;
289 } spi_conf_t;
290 
298 uint32_t periph_apb_clk(uint8_t bus);
299 
307 uint32_t periph_timer_clk(uint8_t bus);
308 
315 void periph_clk_en(bus_t bus, uint32_t mask);
316 
323 void periph_clk_dis(bus_t bus, uint32_t mask);
324 
331 void gpio_init_af(gpio_t pin, gpio_af_t af);
332 
338 void gpio_init_analog(gpio_t pin);
339 
340 #ifdef __cplusplus
341 }
342 #endif
343 
344 #endif /* PERIPH_CPU_COMMON_H */
345 
use alternate function 4
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
use alternate function 7
emit interrupt on rising flank
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
use alternate function 8
use alternate function 10
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
gpio_t pin
pin connected to the line
use alternate function 6
use alternate function 14
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
use alternate function 3
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
use alternate function 1
PWM device configuration.
gpio_af_t af
pin alternate function
emit interrupt on both flanks
use alternate function 0
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
use alternate function 5
static DMA_Stream_TypeDef * dma_stream(int stream)
Get the DMA stream base address.
use alternate function 11
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
gpio_af_t rx_af
alternate function for RX pin
input, no pull
TIM_TypeDef * dev
timer device
DAC line configuration data.
uint32_t rccmask
bit in the RCC peripheral enable register
not supported
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI module configuration options.
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
input, pull-down
gpio_af_t af
alternate function used
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
use alternate function 2
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.