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stm32_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #define CPUID_LEN (12U)
34 
38 #define TIMER_CHAN (4U)
39 
44 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
45 #define PERIPH_SPI_NEEDS_TRANSFER_REG
46 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
47 
52 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(DOXYGEN)
53 #define PM_NUM_MODES (2U)
54 #endif
55 
59 typedef enum {
60  APB1,
61  APB2,
62 #if defined(CPU_FAM_STM32L0)
63  AHB,
64  IOP,
65 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1)\
66  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
67  AHB,
68 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
69  AHB1,
70  AHB2,
71  AHB3
72 #else
73 #warning "unsupported stm32XX family"
74 #endif
75 } bus_t;
76 
77 #ifndef DOXYGEN
78 
82 #define HAVE_GPIO_T
83 typedef uint32_t gpio_t;
85 #endif
86 
90 #define GPIO_UNDEF (0xffffffff)
91 
95 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
96 
103 #define SPI_HWCS_MASK (0xffffff00)
104 
111 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
112 
116 typedef enum {
117 #ifdef CPU_FAM_STM32F1
118  GPIO_AF_OUT_PP = 0xb,
119  GPIO_AF_OUT_OD = 0xf,
120 #else
121  GPIO_AF0 = 0,
129 #ifndef CPU_FAM_STM32F0
138 #endif
139 #endif
140 } gpio_af_t;
141 
142 #ifndef CPU_FAM_STM32F1
143 
151 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
152 
153 #ifndef DOXYGEN
154 
158 #define HAVE_GPIO_MODE_T
159 typedef enum {
160  GPIO_IN = GPIO_MODE(0, 0, 0),
161  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
162  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
163  GPIO_OUT = GPIO_MODE(1, 0, 0),
164  GPIO_OD = GPIO_MODE(1, 0, 1),
165  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
166 } gpio_mode_t;
173 #define HAVE_GPIO_FLANK_T
174 typedef enum {
175  GPIO_RISING = 1,
176  GPIO_FALLING = 2,
177  GPIO_BOTH = 3
178 } gpio_flank_t;
180 #endif /* ndef DOXYGEN */
181 #endif /* ndef CPU_FAM_STM32F1 */
182 
186 typedef struct {
187  TIM_TypeDef *dev;
188  uint32_t max;
189  uint32_t rcc_mask;
190  uint8_t bus;
191  uint8_t irqn;
192 } timer_conf_t;
193 
197 typedef struct {
198  gpio_t pin;
199  uint8_t cc_chan;
200 } pwm_chan_t;
201 
205 typedef struct {
206  TIM_TypeDef *dev;
207  uint32_t rcc_mask;
211  uint8_t bus;
212 } pwm_conf_t;
213 
217 typedef struct {
218  USART_TypeDef *dev;
219  uint32_t rcc_mask;
220  gpio_t rx_pin;
221  gpio_t tx_pin;
222 #ifndef CPU_FAM_STM32F1
225 #endif
226  uint8_t bus;
227  uint8_t irqn;
228 #if 0 /* TODO */
229  uint8_t dma_stream;
230  uint8_t dma_chan;
231 #endif
232 } uart_conf_t;
233 
237 typedef struct {
238  SPI_TypeDef *dev;
239  gpio_t mosi_pin;
240  gpio_t miso_pin;
241  gpio_t sclk_pin;
242  gpio_t cs_pin;
243 #ifndef CPU_FAM_STM32F1
245 #endif
246  uint32_t rccmask;
247  uint8_t apbbus;
248 } spi_conf_t;
249 
257 uint32_t periph_apb_clk(uint8_t bus);
258 
265 void periph_clk_en(bus_t bus, uint32_t mask);
266 
273 void periph_clk_dis(bus_t bus, uint32_t mask);
274 
281 void gpio_init_af(gpio_t pin, gpio_af_t af);
282 
288 void gpio_init_analog(gpio_t pin);
289 
290 #ifdef __cplusplus
291 }
292 #endif
293 
294 #endif /* PERIPH_CPU_COMMON_H */
295 
use alternate function 4
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
use alternate function 7
emit interrupt on rising flank
Definition: gpio.h:114
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
use alternate function 8
use alternate function 10
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
use alternate function 6
use alternate function 14
gpio_af_t
Available MUX values for configuring a pin's alternate function.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
use alternate function 3
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
use alternate function 1
PWM configuration structure.
gpio_af_t af
pin alternate function
emit interrupt on both flanks
Definition: gpio.h:115
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
use alternate function 0
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
Definition: gpio.h:113
use alternate function 5
static DMA_Stream_TypeDef * dma_stream(int stream)
Get the DMA stream base address.
use alternate function 11
input, pull-up
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
gpio_af_t rx_af
alternate function for RX pin
input, no pull
TIM_TypeDef * dev
timer device
uint32_t rccmask
bit in the RCC peripheral enable register
not supported
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI configuration data structure.
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
input, pull-down
gpio_af_t af
alternate function used
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
Timer configuration data.
use alternate function 2
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.