periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
37 #define CLOCK_LSI (37000U)
38 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
39  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
40  defined(CPU_FAM_STM32WB)
41 #define CLOCK_LSI (32000U)
42 #else
43 #error "error: LSI clock speed not defined for your target CPU"
44 #endif
45 
51 #define CPUID_LEN (12U)
52 
56 #define PROVIDES_PM_LAYERED_OFF
57 
61 #define TIMER_CHAN (4U)
62 
66 #define QDEC_CHAN (2U)
67 
72 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
73 #define PERIPH_SPI_NEEDS_TRANSFER_REG
74 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
75 
84 #define PM_NUM_MODES (2U)
85 
90 #define STM32_PM_STOP (1U)
91 #define STM32_PM_STANDBY (0U)
92 
94 #ifndef PM_EWUP_CONFIG
95 
98 #define PM_EWUP_CONFIG (0U)
99 #endif
100 
106 /* Actual Lower Limit is ~100us so round up */
107 #define NWDT_TIME_LOWER_LIMIT (1U)
108 #define NWDT_TIME_UPPER_LIMIT (4U * US_PER_MS * 4096U * (1 << 6U) \
109  / CLOCK_LSI)
110 /* Once enabled wdt can't be stopped */
111 #define WDT_HAS_STOP (0U)
112 #if defined(CPU_FAM_STM32L4)
113 #define WDT_HAS_INIT (1U)
114 #else
115 #define WDT_HAS_INIT (0U)
116 #endif
117 
122 typedef enum {
125 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
126  APB12,
127 #endif
128 #if defined(CPU_FAM_STM32L0)
129  AHB,
130  IOP,
131 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) || \
132  defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
133  AHB,
134 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
135  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
136  defined(CPU_FAM_STM32WB)
137  AHB1,
138  AHB2,
139  AHB3,
140 #else
141 #warning "unsupported stm32XX family"
142 #endif
143 #if defined(CPU_FAM_STM32WB)
144  AHB4,
145 #endif
146 } bus_t;
147 
148 #ifndef DOXYGEN
149 
153 #define HAVE_GPIO_T
154 typedef uint32_t gpio_t;
156 #endif
157 
161 #define GPIO_UNDEF (0xffffffff)
162 
166 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
167 
174 #define SPI_HWCS_MASK (0xffffff00)
175 
182 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
183 
189 #define PERIPH_I2C_NEED_READ_REG
190 
191 #define PERIPH_I2C_NEED_WRITE_REG
192 #define PERIPH_I2C_NEED_READ_REGS
193 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
194  defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4)
195 #define PERIPH_I2C_NEED_WRITE_REGS
196 #endif
197 
202 typedef enum {
203 #ifdef CPU_FAM_STM32F1
204  GPIO_AF_OUT_PP = 0xb,
205  GPIO_AF_OUT_OD = 0xf,
206 #else
207  GPIO_AF0 = 0,
215 #ifndef CPU_FAM_STM32F0
224 #endif
225 #endif
226 } gpio_af_t;
227 
228 #ifndef CPU_FAM_STM32F1
229 
237 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
238 
239 #ifndef DOXYGEN
240 
244 #define HAVE_GPIO_MODE_T
245 typedef enum {
246  GPIO_IN = GPIO_MODE(0, 0, 0),
247  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
248  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
249  GPIO_OUT = GPIO_MODE(1, 0, 0),
250  GPIO_OD = GPIO_MODE(1, 0, 1),
251  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
252 } gpio_mode_t;
259 #define HAVE_GPIO_FLANK_T
260 typedef enum {
261  GPIO_RISING = 1,
262  GPIO_FALLING = 2,
263  GPIO_BOTH = 3
264 } gpio_flank_t;
266 #endif /* ndef DOXYGEN */
267 #endif /* ndef CPU_FAM_STM32F1 */
268 
269 #ifdef MODULE_PERIPH_DMA
270 
273 typedef struct {
296  int stream;
297 } dma_conf_t;
298 
302 typedef unsigned dma_t;
303 
307 typedef enum {
308  DMA_PERIPH_TO_MEM,
309  DMA_MEM_TO_PERIPH,
310  DMA_MEM_TO_MEM,
311 } dma_mode_t;
312 
317 #define DMA_INC_SRC_ADDR (0x01)
318 #define DMA_INC_DST_ADDR (0x02)
319 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
320 
326 #define DMA_DATA_WIDTH_BYTE (0x00)
327 #define DMA_DATA_WIDTH_HALF_WORD (0x04)
328 #define DMA_DATA_WIDTH_WORD (0x08)
329 #define DMA_DATA_WIDTH_MASK (0x0C)
330 #define DMA_DATA_WIDTH_SHIFT (2)
331 
332 #endif /* MODULE_PERIPH_DMA */
333 
337 typedef struct {
338  gpio_t pin;
339  uint8_t chan;
340 } dac_conf_t;
341 
345 typedef struct {
346  TIM_TypeDef *dev;
347  uint32_t max;
348  uint32_t rcc_mask;
349  uint8_t bus;
350  uint8_t irqn;
351 } timer_conf_t;
352 
356 typedef struct {
357  gpio_t pin;
358  uint8_t cc_chan;
359 } pwm_chan_t;
360 
364 typedef struct {
365  TIM_TypeDef *dev;
366  uint32_t rcc_mask;
369  gpio_af_t af;
370  uint8_t bus;
371 } pwm_conf_t;
372 
376 typedef struct {
377  gpio_t pin;
378  uint8_t cc_chan;
379 } qdec_chan_t;
380 
384 typedef struct {
385  TIM_TypeDef *dev;
386  uint32_t max;
387  uint32_t rcc_mask;
390  gpio_af_t af;
391  uint8_t bus;
392  uint8_t irqn;
393 } qdec_conf_t;
394 
398 typedef enum {
401 } uart_type_t;
402 
403 #ifndef DOXYGEN
404 
410 #define UART_INVALID_MODE (0x8000000)
411 
416 #define HAVE_UART_PARITY_T
417 typedef enum {
418  UART_PARITY_NONE = 0,
419  UART_PARITY_EVEN = USART_CR1_PCE,
420  UART_PARITY_ODD = (USART_CR1_PCE | USART_CR1_PS),
421  UART_PARITY_MARK = UART_INVALID_MODE | 4,
422  UART_PARITY_SPACE = UART_INVALID_MODE | 5
423 } uart_parity_t;
430 #define HAVE_UART_DATA_BITS_T
431 typedef enum {
432  UART_DATA_BITS_5 = UART_INVALID_MODE | 1,
433  UART_DATA_BITS_6 = UART_INVALID_MODE | 2,
434 #if defined(USART_CR1_M1)
435  UART_DATA_BITS_7 = USART_CR1_M1,
436 #else
437  UART_DATA_BITS_7 = UART_INVALID_MODE | 3,
438 #endif
439  UART_DATA_BITS_8 = 0,
447 #define HAVE_UART_STOP_BITS_T
448 typedef enum {
449  UART_STOP_BITS_1 = 0,
450  UART_STOP_BITS_2 = USART_CR2_STOP_1,
453 #endif /* ndef DOXYGEN */
454 
458 typedef struct {
459  USART_TypeDef *dev;
460  uint32_t rcc_mask;
461  gpio_t rx_pin;
462  gpio_t tx_pin;
463 #ifndef CPU_FAM_STM32F1
464  gpio_af_t rx_af;
465  gpio_af_t tx_af;
466 #endif
467  uint8_t bus;
468  uint8_t irqn;
469 #ifdef MODULE_PERIPH_UART_HW_FC
470  gpio_t cts_pin;
471  gpio_t rts_pin;
472 #ifndef CPU_FAM_STM32F1
473  gpio_af_t cts_af;
474  gpio_af_t rts_af;
475 #endif
476 #endif
477 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
478  defined(CPU_FAM_STM32WB)
479  uart_type_t type;
480  uint32_t clk_src;
481 #endif
482 #ifdef MODULE_PERIPH_DMA
483  dma_t dma;
484  uint8_t dma_chan;
485 #endif
486 } uart_conf_t;
487 
491 typedef struct {
492  SPI_TypeDef *dev;
493  gpio_t mosi_pin;
494  gpio_t miso_pin;
495  gpio_t sclk_pin;
496  gpio_t cs_pin;
497 #ifndef CPU_FAM_STM32F1
498  gpio_af_t mosi_af;
499  gpio_af_t miso_af;
500  gpio_af_t sclk_af;
501  gpio_af_t cs_af;
502 #endif
503  uint32_t rccmask;
504  uint8_t apbbus;
505 #ifdef MODULE_PERIPH_DMA
506  dma_t tx_dma;
507  uint8_t tx_dma_chan;
508  dma_t rx_dma;
509  uint8_t rx_dma_chan;
510 #endif
511 } spi_conf_t;
512 
513 #ifndef DOXYGEN
514 
518 #define HAVE_I2C_SPEED_T
519 typedef enum {
520 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
521  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
522  I2C_SPEED_LOW,
523 #endif
526 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
527  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
528  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
530 #endif
531 } i2c_speed_t;
533 #endif /* ndef DOXYGEN */
534 
538 typedef struct {
539  I2C_TypeDef *dev;
540  i2c_speed_t speed;
541  gpio_t scl_pin;
542  gpio_t sda_pin;
543 #ifndef CPU_FAM_STM32F1
544  gpio_af_t scl_af;
545  gpio_af_t sda_af;
546 #endif
547  uint8_t bus;
548  uint32_t rcc_mask;
549 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
550  uint32_t rcc_sw_mask;
551 #endif
552 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
553  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
554  uint32_t clk;
555 #endif
556  uint8_t irqn;
557 } i2c_conf_t;
558 
559 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
560  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
561  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB)
562 
573 typedef struct {
574  uint8_t presc;
575  uint8_t scll;
576  uint8_t sclh;
577  uint8_t sdadel;
578  uint8_t scldel;
579 } i2c_timing_param_t;
580 #endif
581 
591 typedef enum {
595 
602 typedef enum {
603  STM32_USB_OTG_PHY_BUILTIN,
604  STM32_USB_OTG_PHY_ULPI,
606 
610 typedef struct {
611  uint8_t *periph;
612  uint32_t rcc_mask;
613  stm32_usb_otg_fshs_phy_t phy;
615  uint8_t irqn;
616  uint8_t ahb;
617  gpio_t dm;
618  gpio_t dp;
619  gpio_af_t af;
621 
629 uint32_t periph_apb_clk(uint8_t bus);
630 
638 uint32_t periph_timer_clk(uint8_t bus);
639 
646 void periph_clk_en(bus_t bus, uint32_t mask);
647 
654 void periph_lpclk_dis(bus_t bus, uint32_t mask);
655 
662 void periph_lpclk_en(bus_t bus, uint32_t mask);
663 
670 void periph_clk_dis(bus_t bus, uint32_t mask);
671 
678 void gpio_init_af(gpio_t pin, gpio_af_t af);
679 
685 void gpio_init_analog(gpio_t pin);
686 
687 #ifdef MODULE_PERIPH_DMA
688 
691 #define DMA_STREAM_UNDEF (UINT_MAX)
692 
696 void dma_init(void);
697 
714 int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
715  dma_mode_t mode, uint8_t flags);
716 
722 void dma_acquire(dma_t dma);
723 
729 void dma_release(dma_t dma);
730 
739 void dma_start(dma_t dma);
740 
748 uint16_t dma_suspend(dma_t dma);
749 
756 void dma_resume(dma_t dma, uint16_t remaining);
757 
763 void dma_stop(dma_t dma);
764 
770 void dma_wait(dma_t dma);
771 
785 int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
786  dma_mode_t mode, uint8_t flags);
787 
788 #endif /* MODULE_PERIPH_DMA */
789 
790 #ifdef MODULE_PERIPH_CAN
791 #include "candev_stm32.h"
792 #endif
793 
794 #ifdef MODULE_PERIPH_USBDEV
795 #include "usbdev_stm32.h"
796 #endif
797 
801 typedef enum {
802  MII = 18,
803  RMII = 9,
804  SMI = 2,
805 } eth_mode_t;
806 
810 typedef enum {
811  ETH_SPEED_10T_HD = 0x0000,
812  ETH_SPEED_10T_FD = 0x0100,
813  ETH_SPEED_100TX_HD = 0x2000,
814  ETH_SPEED_100TX_FD = 0x2100,
815 } eth_speed_t;
816 
820 typedef struct {
822  char mac[6];
824  uint8_t dma;
825  uint8_t dma_chan;
826  char phy_addr;
827  gpio_t pins[];
830 } eth_conf_t;
831 
836 #define PHY_BMCR (0x00)
837 #define PHY_BSMR (0x01)
838 #define PHY_PHYIDR1 (0x02)
839 #define PHY_PHYIDR2 (0x03)
840 #define PHY_ANAR (0x04)
841 #define PHY_ANLPAR (0x05)
842 #define PHY_ANER (0x06)
843 #define PHY_ANNPTR (0x07)
844 
850 #define BMCR_RESET (0x8000)
851 #define BMCR_LOOPBACK (0x4000)
852 #define BMCR_SPEED_SELECT (0x2000)
853 #define BMCR_AN (0x1000)
854 #define BMCR_POWER_DOWN (0x0800)
855 #define BMCR_ISOLATE (0x0400)
856 #define BMCR_RESTART_AN (0x0200)
857 #define BMCR_DUPLEX_MODE (0x0100)
858 #define BMCR_COLLISION_TEST (0x0080)
859 
865 #define BSMR_100BASE_T4 (0x8000)
866 #define BSMR_100BASE_TX_FDUPLEX (0x4000)
867 #define BSMR_100BASE_TX_HDUPLEX (0x2000)
868 #define BSMR_10BASE_T_FDUPLEX (0x1000)
869 #define BSMR_10BASE_T_HDUPLEX (0x0800)
870 #define BSMR_NO_PREAMBLE (0x0040)
871 #define BSMR_AN_COMPLETE (0x0020)
872 #define BSMR_REMOTE_FAULT (0x0010)
873 #define BSMR_AN_ABILITY (0x0008)
874 #define BSMR_LINK_STATUS (0x0004)
875 #define BSMR_JABBER_DETECT (0x0002)
876 #define BSMR_EXTENDED_CAP (0x0001)
877 
882 #define PHYIDR1_OUI (0xffff)
883 
888 #define PHYIDR2_OUI (0xfe00)
889 #define PHYIDR2_MODEL (0x01f0)
890 #define PHYIDR2_REV (0x0007)
891 
897 #define ANAR_NEXT_PAGE (0x8000)
898 #define ANAR_REMOTE_FAULT (0x2000)
899 #define ANAR_PAUSE (0x0600)
900 #define ANAR_100BASE_T4 (0x0200)
901 #define ANAR_100BASE_TX_FDUPLEX (0x0100)
902 #define ANAR_100BASE_TX_HDUPLEX (0x0080)
903 #define ANAR_10BASE_T_FDUPLEX (0x0040)
904 #define ANAR_10BASE_T_HDUPLEX (0x0020)
905 #define ANAR_SELECTOR (0x000f)
906 
912 #define ANLPAR_NEXT_PAGE (0x8000)
913 #define ANLPAR_ACK (0x4000)
914 #define ANLPAR_REMOTE_FAULT (0x2000)
915 #define ANLPAR_PAUSE (0x0600)
916 #define ANLPAR_100BASE_T4 (0x0200)
917 #define ANLPAR_100BASE_TX_FDUPLEX (0x0100)
918 #define ANLPAR_100BASE_TX_HDUPLEX (0x0080)
919 #define ANLPAR_10BASE_T_FDUPLEX (0x0040)
920 #define ANLPAR_10BASE_T_HDUPLEX (0x0020)
921 #define ANLPAR_SELECTOR (0x000f)
922 
928 #define ANNPTR_NEXT_PAGE (0x8000)
929 #define ANNPTR_MSG_PAGE (0x2000)
930 #define ANNPTR_ACK2 (0x1000)
931 #define ANNPTR_TOGGLE_TX (0x0800)
932 #define ANNPTR_CODE (0x03ff)
933 
939 #define ANER_PDF (0x0010)
940 #define ANER_LP_NEXT_PAGE_ABLE (0x0008)
941 #define ANER_NEXT_PAGE_ABLE (0x0004)
942 #define ANER_PAGE_RX (0x0002)
943 #define ANER_LP_AN_ABLE (0x0001)
944 
946 #ifdef MODULE_STM32_ETH
947 
955 int32_t stm32_eth_phy_read(uint16_t addr, uint8_t reg);
956 
966 int32_t stm32_eth_phy_write(uint16_t addr, uint8_t reg, uint16_t value);
967 #endif /* MODULE_STM32_ETH */
968 
969 #ifdef __cplusplus
970 }
971 #endif
972 
973 #endif /* PERIPH_CPU_COMMON_H */
974 
fast mode: ~400 kbit/s
Definition: i2c.h:184
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
gpio_af_t miso_af
MISO pin alternate function.
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
configure as output in push-pull mode
Definition: gpio.h:117
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:141
High speed peripheral.
bxCAN specific definitions
stm32_usb_otg_fshs_type_t
USB OTG peripheral type.
I2C configuration options.
Definition: periph_cpu.h:128
emit interrupt on rising flank
Definition: gpio.h:131
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
eth_speed_t
STM32 Ethernet speed options.
odd parity
Definition: uart.h:131
uint8_t bus
APB bus.
uint32_t rcc_mask
bit in clock enable register
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
uint8_t bus
APB bus.
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
use alternate function 9
gpio_t pin
pin connected to the line
gpio_af_t sclk_af
SCLK pin alternate function.
mark parity
Definition: uart.h:132
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
uint32_t rcc_mask
bit in clock enable register
use alternate function 13
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:153
APB1 bus.
TIM_TypeDef * dev
Timer used.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
gpio_t sclk_pin
SCLK pin.
uart_type_t
UART hardware module types.
gpio_t pin
GPIO pin mapped to this channel.
uint8_t bus
APBx bus the timer is clock from.
uint8_t bus
APB bus.
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:181
gpio_af_t af
alternate function used
uint8_t irqn
global IRQ channel
gpio_af_t mosi_af
MOSI pin alternate function.
space parity
Definition: uart.h:133
PWM channel.
eth_mode_t mode
Select configuration mode.
use alternate function 11
use alternate function 8
stm32 USB OTG configuration
PWM device configuration.
no parity
Definition: uart.h:129
emit interrupt on both flanks
Definition: gpio.h:132
uint32_t max
Maximum counter value.
5 data bits
Definition: uart.h:142
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
uint8_t dma
Locical CMA Descriptor used for TX.
use alternate function 1
use alternate function 10
eth_mode_t
STM32 Ethernet configuration mode.
char phy_addr
PHY address.
uint8_t dma_chan
DMA channel used for TX.
use alternate function 5
STM32 Low-power UART (LPUART) module type.
QDEC channel.
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:128
1 stop bit
Definition: uart.h:154
use alternate function 2
even parity
Definition: uart.h:130
7 data bits
Definition: uart.h:144
USB interface functions for the stm32 OTG FS/HS class devices.
2 stop bits
Definition: uart.h:155
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
STM32 USART module type.
TIM_TypeDef * dev
Timer used.
use alternate function 6
uint8_t * periph
USB peripheral base address.
use alternate function 12
gpio_af_t cs_af
HWCS pin alternate function.
use alternate function 4
uint32_t rcc_mask
bit in clock enable register
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
Definition: gpio.h:130
eth_speed_t speed
Speed selection.
stm32_usb_otg_fshs_type_t type
FS or HS type.
8 data bits
Definition: uart.h:145
APB2 bus.
gpio_af_t scl_af
scl pin alternate function value
gpio_af_t af
Alternative function.
6 data bits
Definition: uart.h:143
configure as input with pull-up resistor
Definition: gpio.h:116
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 0
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
TIM_TypeDef * dev
timer device
stm32_usb_otg_fshs_phy_t
Type of USB OTG peripheral phy.
DAC line configuration data.
Full speed peripheral.
uint32_t rccmask
bit in the RCC peripheral enable register
Configuration for SMI.
uint8_t bus
APB bus.
Configuration for MII.
low speed mode: ~10 kbit/s
Definition: i2c.h:182
uint8_t irqn
I2C event interrupt number.
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
stm32_usb_otg_fshs_phy_t phy
Built-in or ULPI phy.
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
SPI configuration structure type.
Definition: periph_cpu.h:273
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
normal mode: ~100 kbit/s
Definition: i2c.h:183
configure as input with pull-down resistor
Definition: gpio.h:115
gpio_af_t sda_af
sda pin alternate function value
use alternate function 14
use alternate function 15
gpio_af_t af
alternate function used
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
Ethernet Peripheral configuration.
Configuration for RMII.
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
Definition: periph_cpu.h:288
use alternate function 3
use alternate function 7
fast plus mode: ~1000 kbit/s
Definition: i2c.h:185
uint8_t cc_chan
capture compare channel used
QDEC configuration.
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.