periph_cpu_common.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
34  defined(CPU_FAM_STM32F3)
35 #define CLOCK_LSI (40000U)
36 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
37 #define CLOCK_LSI (37000U)
38 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
39  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
40 #define CLOCK_LSI (32000U)
41 #else
42 #error "error: LSI clock speed not defined for your target CPU"
43 #endif
44 
50 #define CPUID_LEN (12U)
51 
55 #define PROVIDES_PM_LAYERED_OFF
56 
60 #define TIMER_CHAN (4U)
61 
65 #define QDEC_CHAN (2U)
66 
71 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
72 #define PERIPH_SPI_NEEDS_TRANSFER_REG
73 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
74 
83 #define PM_NUM_MODES (2U)
84 
89 #define STM32_PM_STOP (1U)
90 #define STM32_PM_STANDBY (0U)
91 
93 #ifndef PM_EWUP_CONFIG
94 
97 #define PM_EWUP_CONFIG (0U)
98 #endif
99 
105 /* Actual Lower Limit is ~100us so round up */
106 #define NWDT_TIME_LOWER_LIMIT (1U)
107 #define NWDT_TIME_UPPER_LIMIT (4U * US_PER_MS * 4096U * (1 << 6U) \
108  / CLOCK_LSI)
109 /* Once enabled wdt can't be stopped */
110 #define WDT_HAS_STOP (0U)
111 #if defined(CPU_FAM_STM32L4)
112 #define WDT_HAS_INIT (1U)
113 #else
114 #define WDT_HAS_INIT (0U)
115 #endif
116 
121 typedef enum {
124 #if defined(CPU_FAM_STM32L4)
125  APB12,
126 #endif
127 #if defined(CPU_FAM_STM32L0)
128  AHB,
129  IOP,
130 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
131  || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
132  AHB,
133 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
134  || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
135  AHB1,
136  AHB2,
137  AHB3
138 #else
139 #warning "unsupported stm32XX family"
140 #endif
141 } bus_t;
142 
143 #ifndef DOXYGEN
144 
148 #define HAVE_GPIO_T
149 typedef uint32_t gpio_t;
151 #endif
152 
156 #define GPIO_UNDEF (0xffffffff)
157 
161 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
162 
169 #define SPI_HWCS_MASK (0xffffff00)
170 
177 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
178 
184 #define PERIPH_I2C_NEED_READ_REG
185 
186 #define PERIPH_I2C_NEED_WRITE_REG
187 #define PERIPH_I2C_NEED_READ_REGS
188 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
189  defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4)
190 #define PERIPH_I2C_NEED_WRITE_REGS
191 #endif
192 
197 typedef enum {
198 #ifdef CPU_FAM_STM32F1
199  GPIO_AF_OUT_PP = 0xb,
200  GPIO_AF_OUT_OD = 0xf,
201 #else
202  GPIO_AF0 = 0,
210 #ifndef CPU_FAM_STM32F0
219 #endif
220 #endif
221 } gpio_af_t;
222 
223 #ifndef CPU_FAM_STM32F1
224 
232 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
233 
234 #ifndef DOXYGEN
235 
239 #define HAVE_GPIO_MODE_T
240 typedef enum {
241  GPIO_IN = GPIO_MODE(0, 0, 0),
242  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
243  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
244  GPIO_OUT = GPIO_MODE(1, 0, 0),
245  GPIO_OD = GPIO_MODE(1, 0, 1),
246  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
247 } gpio_mode_t;
254 #define HAVE_GPIO_FLANK_T
255 typedef enum {
256  GPIO_RISING = 1,
257  GPIO_FALLING = 2,
258  GPIO_BOTH = 3
259 } gpio_flank_t;
261 #endif /* ndef DOXYGEN */
262 #endif /* ndef CPU_FAM_STM32F1 */
263 
264 #ifdef MODULE_PERIPH_DMA
265 
268 typedef struct {
291  int stream;
292 } dma_conf_t;
293 
297 typedef unsigned dma_t;
298 
302 typedef enum {
303  DMA_PERIPH_TO_MEM,
304  DMA_MEM_TO_PERIPH,
305  DMA_MEM_TO_MEM,
306 } dma_mode_t;
307 
312 #define DMA_INC_SRC_ADDR (0x01)
313 #define DMA_INC_DST_ADDR (0x02)
314 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
315 
321 #define DMA_DATA_WIDTH_BYTE (0x00)
322 #define DMA_DATA_WIDTH_HALF_WORD (0x04)
323 #define DMA_DATA_WIDTH_WORD (0x08)
324 #define DMA_DATA_WIDTH_MASK (0x0C)
325 #define DMA_DATA_WIDTH_SHIFT (2)
326 
327 #endif /* MODULE_PERIPH_DMA */
328 
332 typedef struct {
333  gpio_t pin;
334  uint8_t chan;
335 } dac_conf_t;
336 
340 typedef struct {
341  TIM_TypeDef *dev;
342  uint32_t max;
343  uint32_t rcc_mask;
344  uint8_t bus;
345  uint8_t irqn;
346 } timer_conf_t;
347 
351 typedef struct {
352  gpio_t pin;
353  uint8_t cc_chan;
354 } pwm_chan_t;
355 
359 typedef struct {
360  TIM_TypeDef *dev;
361  uint32_t rcc_mask;
364  gpio_af_t af;
365  uint8_t bus;
366 } pwm_conf_t;
367 
371 typedef struct {
372  gpio_t pin;
373  uint8_t cc_chan;
374 } qdec_chan_t;
375 
379 typedef struct {
380  TIM_TypeDef *dev;
381  uint32_t max;
382  uint32_t rcc_mask;
385  gpio_af_t af;
386  uint8_t bus;
387  uint8_t irqn;
388 } qdec_conf_t;
389 
393 typedef enum {
396 } uart_type_t;
397 
398 #ifndef DOXYGEN
399 
405 #define UART_INVALID_MODE (0x8000000)
406 
411 #define HAVE_UART_PARITY_T
412 typedef enum {
413  UART_PARITY_NONE = 0,
414  UART_PARITY_EVEN = USART_CR1_PCE,
415  UART_PARITY_ODD = (USART_CR1_PCE | USART_CR1_PS),
416  UART_PARITY_MARK = UART_INVALID_MODE | 4,
417  UART_PARITY_SPACE = UART_INVALID_MODE | 5
418 } uart_parity_t;
425 #define HAVE_UART_DATA_BITS_T
426 typedef enum {
427  UART_DATA_BITS_5 = UART_INVALID_MODE | 1,
428  UART_DATA_BITS_6 = UART_INVALID_MODE | 2,
429 #if defined(USART_CR1_M1)
430  UART_DATA_BITS_7 = USART_CR1_M1,
431 #else
432  UART_DATA_BITS_7 = UART_INVALID_MODE | 3,
433 #endif
434  UART_DATA_BITS_8 = 0,
442 #define HAVE_UART_STOP_BITS_T
443 typedef enum {
444  UART_STOP_BITS_1 = 0,
445  UART_STOP_BITS_2 = USART_CR2_STOP_1,
448 #endif /* ndef DOXYGEN */
449 
453 typedef struct {
454  USART_TypeDef *dev;
455  uint32_t rcc_mask;
456  gpio_t rx_pin;
457  gpio_t tx_pin;
458 #ifndef CPU_FAM_STM32F1
459  gpio_af_t rx_af;
460  gpio_af_t tx_af;
461 #endif
462  uint8_t bus;
463  uint8_t irqn;
464 #ifdef MODULE_STM32_PERIPH_UART_HW_FC
465  gpio_t cts_pin;
466  gpio_t rts_pin;
467 #ifndef CPU_FAM_STM32F1
468  gpio_af_t cts_af;
469  gpio_af_t rts_af;
470 #endif
471 #endif
472 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4)
473  uart_type_t type;
474  uint32_t clk_src;
475 #endif
476 #ifdef MODULE_PERIPH_DMA
477  dma_t dma;
478  uint8_t dma_chan;
479 #endif
480 } uart_conf_t;
481 
485 typedef struct {
486  SPI_TypeDef *dev;
487  gpio_t mosi_pin;
488  gpio_t miso_pin;
489  gpio_t sclk_pin;
490  gpio_t cs_pin;
491 #ifndef CPU_FAM_STM32F1
492  gpio_af_t af;
493 #endif
494  uint32_t rccmask;
495  uint8_t apbbus;
496 #ifdef MODULE_PERIPH_DMA
497  dma_t tx_dma;
498  uint8_t tx_dma_chan;
499  dma_t rx_dma;
500  uint8_t rx_dma_chan;
501 #endif
502 } spi_conf_t;
503 
508 #define HAVE_I2C_SPEED_T
509 typedef enum {
510 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
511  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
512  I2C_SPEED_LOW,
513 #endif
516 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
517  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
518  defined(CPU_FAM_STM32L4)
520 #endif
521 } i2c_speed_t;
527 typedef struct {
528  I2C_TypeDef *dev;
529  i2c_speed_t speed;
530  gpio_t scl_pin;
531  gpio_t sda_pin;
532 #ifndef CPU_FAM_STM32F1
533  gpio_af_t scl_af;
534  gpio_af_t sda_af;
535 #endif
536  uint8_t bus;
537  uint32_t rcc_mask;
538 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
539  uint32_t rcc_sw_mask;
540 #endif
541 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
542  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1)
543  uint32_t clk;
544 #endif
545  uint8_t irqn;
546 } i2c_conf_t;
547 
548 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
549  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
550  defined(CPU_FAM_STM32L4)
551 
562 typedef struct {
563  uint8_t presc;
564  uint8_t scll;
565  uint8_t sclh;
566  uint8_t sdadel;
567  uint8_t scldel;
568 } i2c_timing_param_t;
569 #endif
570 
578 uint32_t periph_apb_clk(uint8_t bus);
579 
587 uint32_t periph_timer_clk(uint8_t bus);
588 
595 void periph_clk_en(bus_t bus, uint32_t mask);
596 
603 void periph_clk_dis(bus_t bus, uint32_t mask);
604 
611 void gpio_init_af(gpio_t pin, gpio_af_t af);
612 
618 void gpio_init_analog(gpio_t pin);
619 
620 #ifdef MODULE_PERIPH_DMA
621 
624 #define DMA_STREAM_UNDEF (UINT_MAX)
625 
629 void dma_init(void);
630 
647 int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
648  dma_mode_t mode, uint8_t flags);
649 
655 void dma_acquire(dma_t dma);
656 
662 void dma_release(dma_t dma);
663 
672 void dma_start(dma_t dma);
673 
681 uint16_t dma_suspend(dma_t dma);
682 
689 void dma_resume(dma_t dma, uint16_t remaining);
690 
696 void dma_stop(dma_t dma);
697 
703 void dma_wait(dma_t dma);
704 
718 int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
719  dma_mode_t mode, uint8_t flags);
720 
721 #endif /* MODULE_PERIPH_DMA */
722 
723 #ifdef MODULE_PERIPH_CAN
724 #include "candev_stm32.h"
725 #endif
726 
730 typedef enum {
731  MII = 18,
732  RMII = 9,
733  SMI = 2,
734 } eth_mode_t;
735 
739 typedef enum {
740  ETH_SPEED_10T_HD = 0x0000,
741  ETH_SPEED_10T_FD = 0x0100,
742  ETH_SPEED_100TX_HD = 0x2000,
743  ETH_SPEED_100TX_FD = 0x2100,
744 } eth_speed_t;
745 
749 typedef struct {
751  char mac[6];
753  uint8_t dma;
754  uint8_t dma_chan;
755  char phy_addr;
756  gpio_t pins[];
759 } eth_conf_t;
760 
765 #define PHY_BMCR (0x00)
766 #define PHY_BSMR (0x01)
767 #define PHY_PHYIDR1 (0x02)
768 #define PHY_PHYIDR2 (0x03)
769 #define PHY_ANAR (0x04)
770 #define PHY_ANLPAR (0x05)
771 #define PHY_ANER (0x06)
772 #define PHY_ANNPTR (0x07)
773 
779 #define BMCR_RESET (0x8000)
780 #define BMCR_LOOPBACK (0x4000)
781 #define BMCR_SPEED_SELECT (0x2000)
782 #define BMCR_AN (0x1000)
783 #define BMCR_POWER_DOWN (0x0800)
784 #define BMCR_ISOLATE (0x0400)
785 #define BMCR_RESTART_AN (0x0200)
786 #define BMCR_DUPLEX_MODE (0x0100)
787 #define BMCR_COLLISION_TEST (0x0080)
788 
794 #define BSMR_100BASE_T4 (0x8000)
795 #define BSMR_100BASE_TX_FDUPLEX (0x4000)
796 #define BSMR_100BASE_TX_HDUPLEX (0x2000)
797 #define BSMR_10BASE_T_FDUPLEX (0x1000)
798 #define BSMR_10BASE_T_HDUPLEX (0x0800)
799 #define BSMR_NO_PREAMBLE (0x0040)
800 #define BSMR_AN_COMPLETE (0x0020)
801 #define BSMR_REMOTE_FAULT (0x0010)
802 #define BSMR_AN_ABILITY (0x0008)
803 #define BSMR_LINK_STATUS (0x0004)
804 #define BSMR_JABBER_DETECT (0x0002)
805 #define BSMR_EXTENDED_CAP (0x0001)
806 
811 #define PHYIDR1_OUI (0xffff)
812 
817 #define PHYIDR2_OUI (0xfe00)
818 #define PHYIDR2_MODEL (0x01f0)
819 #define PHYIDR2_REV (0x0007)
820 
826 #define ANAR_NEXT_PAGE (0x8000)
827 #define ANAR_REMOTE_FAULT (0x2000)
828 #define ANAR_PAUSE (0x0600)
829 #define ANAR_100BASE_T4 (0x0200)
830 #define ANAR_100BASE_TX_FDUPLEX (0x0100)
831 #define ANAR_100BASE_TX_HDUPLEX (0x0080)
832 #define ANAR_10BASE_T_FDUPLEX (0x0040)
833 #define ANAR_10BASE_T_HDUPLEX (0x0020)
834 #define ANAR_SELECTOR (0x000f)
835 
841 #define ANLPAR_NEXT_PAGE (0x8000)
842 #define ANLPAR_ACK (0x4000)
843 #define ANLPAR_REMOTE_FAULT (0x2000)
844 #define ANLPAR_PAUSE (0x0600)
845 #define ANLPAR_100BASE_T4 (0x0200)
846 #define ANLPAR_100BASE_TX_FDUPLEX (0x0100)
847 #define ANLPAR_100BASE_TX_HDUPLEX (0x0080)
848 #define ANLPAR_10BASE_T_FDUPLEX (0x0040)
849 #define ANLPAR_10BASE_T_HDUPLEX (0x0020)
850 #define ANLPAR_SELECTOR (0x000f)
851 
857 #define ANNPTR_NEXT_PAGE (0x8000)
858 #define ANNPTR_MSG_PAGE (0x2000)
859 #define ANNPTR_ACK2 (0x1000)
860 #define ANNPTR_TOGGLE_TX (0x0800)
861 #define ANNPTR_CODE (0x03ff)
862 
868 #define ANER_PDF (0x0010)
869 #define ANER_LP_NEXT_PAGE_ABLE (0x0008)
870 #define ANER_NEXT_PAGE_ABLE (0x0004)
871 #define ANER_PAGE_RX (0x0002)
872 #define ANER_LP_AN_ABLE (0x0001)
873 
875 #ifdef MODULE_STM32_ETH
876 
884 int32_t stm32_eth_phy_read(uint16_t addr, uint8_t reg);
885 
895 int32_t stm32_eth_phy_write(uint16_t addr, uint8_t reg, uint16_t value);
896 #endif /* MODULE_STM32_ETH */
897 
898 #ifdef __cplusplus
899 }
900 #endif
901 
902 #endif /* PERIPH_CPU_COMMON_H */
903 
use alternate function 4
gpio_flank_t
fast mode: ~400kbit/s
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
use alternate function 9
output
Definition: periph_cpu.h:151
use alternate function 7
bxCAN specific definitions
I2C configuration options.
Definition: periph_cpu.h:125
emit interrupt on rising flank
i2c_speed_t
bus_t
Available peripheral buses.
uint32_t rcc_mask
bit in clock enable register
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
use alternate function 8
eth_speed_t
STM32 Ethernet speed options.
odd parity
Definition: uart.h:131
uint8_t bus
APB bus.
uint32_t rcc_mask
bit in clock enable register
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
use alternate function 10
uint8_t bus
APB bus.
uint32_t rcc_mask
corresponding bit in the RCC register
uint32_t max
maximum value to count to (16/32 bit)
uint8_t cc_chan
capture compare channel used
gpio_t pin
pin connected to the line
use alternate function 6
use alternate function 14
mark parity
Definition: uart.h:132
uint32_t rcc_mask
bit in clock enable register
gpio_af_t
Available MUX values for configuring a pin&#39;s alternate function.
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:153
APB1 bus.
TIM_TypeDef * dev
Timer used.
#define TIMER_CHAN
All STM timers have 4 capture-compare channels.
gpio_t sclk_pin
SCLK pin.
uart_type_t
UART hardware module types.
use alternate function 3
gpio_t pin
GPIO pin mapped to this channel.
uint8_t bus
APBx bus the timer is clock from.
gpio_af_t tx_af
alternate function for TX pin
uint8_t bus
APB bus.
gpio_af_t af
alternate function used
uint8_t irqn
global IRQ channel
space parity
Definition: uart.h:133
PWM channel.
use alternate function 1
eth_mode_t mode
Select configuration mode.
PWM configuration.
gpio_af_t af
pin alternate function
no parity
Definition: uart.h:129
emit interrupt on both flanks
uart_data_bits_t
uint32_t max
Maximum counter value.
uint8_t dma
Locical CMA Descriptor used for TX.
gpio_mode_t
Definition: periph_cpu.h:146
eth_mode_t
STM32 Ethernet configuration mode.
char phy_addr
PHY address.
uint8_t dma_chan
DMA channel used for TX.
STM32 Low-power UART (LPUART) module type.
QDEC channel.
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:128
1 stop bit
Definition: uart.h:154
use alternate function 0
even parity
Definition: uart.h:130
2 stop bits
Definition: uart.h:155
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
STM32 USART module type.
use alternate function 13
TIM_TypeDef * dev
Timer used.
uint32_t rcc_mask
bit in clock enable register
emit interrupt on falling flank
eth_speed_t speed
Speed selection.
APB2 bus.
gpio_af_t scl_af
scl pin alternate function value
use alternate function 5
use alternate function 11
input, pull-up
Definition: periph_cpu.h:150
uint8_t apbbus
APBx bus the device is connected to.
use alternate function 12
void gpio_init_af(gpio_t pin, gpio_af_t af)
Configure the alternate function for the given pin.
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
UART device configuration.
Definition: periph_cpu.h:162
gpio_af_t rx_af
alternate function for RX pin
input, no pull
Definition: periph_cpu.h:147
TIM_TypeDef * dev
timer device
DAC line configuration data.
uint32_t rccmask
bit in the RCC peripheral enable register
Configuration for SMI.
uint8_t bus
APB bus.
Configuration for MII.
low speed mode: ~10kbit/s
uint8_t irqn
I2C event interrupt number.
not supported
Definition: periph_cpu.h:152
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
use alternate function 15
SPI configuration structure type.
Definition: periph_cpu.h:267
SPI_TypeDef * dev
SPI device base register address.
gpio_t pin
GPIO pin mapped to this channel.
normal mode: ~100kbit/s
input, pull-down
Definition: periph_cpu.h:149
gpio_af_t sda_af
sda pin alternate function value
gpio_af_t af
alternate function used
not supported
Definition: periph_cpu.h:153
Ethernet Peripheral configuration.
Configuration for RMII.
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
uint8_t chan
DAC device used for this line.
Timer configuration.
Definition: periph_cpu.h:282
use alternate function 2
fast plus mode: ~1Mbit/s
uint8_t cc_chan
capture compare channel used
QDEC configuration.
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.