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periph_cpu.h
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1/*
2 * Copyright (C) 2019 ML!PA Consulting GmbH
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef PERIPH_CPU_H
21#define PERIPH_CPU_H
22
23#include <limits.h>
24
25#include "macros/units.h"
26#include "periph_cpu_common.h"
27
28#include "candev_samd5x.h"
29#ifdef __cplusplus
30extern "C" {
31#endif
32
36#define SAM0_DFLL_FREQ_HZ MHZ(48)
37
41#define SAM0_XOSC_FREQ_HZ (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)
42
46#define SAM0_DPLL_FREQ_MIN_HZ MHZ(96)
47
51#define SAM0_DPLL_FREQ_MAX_HZ MHZ(200)
52
57#define PM_NUM_MODES (4)
62enum {
63 SAM0_PM_BACKUP = 0,
64 SAM0_PM_HIBERNATE = 1,
65 SAM0_PM_STANDBY = 2,
66 SAM0_PM_IDLE = 3,
67};
74#define SAM0_GCLK_MAIN 0
75#ifndef SAM0_GCLK_32KHZ
76#define SAM0_GCLK_32KHZ 1
77#endif
78#ifndef SAM0_GCLK_TIMER
79#define SAM0_GCLK_TIMER 2
80#endif
81#ifndef SAM0_GCLK_PERIPH
82#define SAM0_GCLK_PERIPH 3
83#endif
84#ifndef SAM0_GCLK_100MHZ
85#define SAM0_GCLK_100MHZ 4
86#endif
93#define SAM0_GCLK_8MHZ SAM0_GCLK_TIMER
94#define SAM0_GCLK_48MHZ SAM0_GCLK_PERIPH
102#define SPI_HWCS(x) (UINT_MAX - 1)
103
107static const gpio_t sam0_adc_pins[2][16] = {
108 { /* ADC0 pins */
109 GPIO_PIN(PA, 2), GPIO_PIN(PA, 3), GPIO_PIN(PB, 8), GPIO_PIN(PB, 9),
110 GPIO_PIN(PA, 4), GPIO_PIN(PA, 5), GPIO_PIN(PA, 6), GPIO_PIN(PA, 7),
111 GPIO_PIN(PA, 8), GPIO_PIN(PA, 9), GPIO_PIN(PA, 10), GPIO_PIN(PA, 11),
112 GPIO_PIN(PB, 0), GPIO_PIN(PB, 1), GPIO_PIN(PB, 2), GPIO_PIN(PB, 3)
113 },
114 { /* ADC1 pins */
115 GPIO_PIN(PB, 8), GPIO_PIN(PB, 9), GPIO_PIN(PA, 8), GPIO_PIN(PA, 9),
116 GPIO_PIN(PC, 2), GPIO_PIN(PC, 3), GPIO_PIN(PB, 4), GPIO_PIN(PB, 5),
117 GPIO_PIN(PB, 6), GPIO_PIN(PB, 7), GPIO_PIN(PC, 0), GPIO_PIN(PC, 1),
118 GPIO_PIN(PC, 30), GPIO_PIN(PC, 31), GPIO_PIN(PD, 0), GPIO_PIN(PD, 1)
119 }
120};
121
126#define ADC0_INPUTCTRL_MUXPOS_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
127#define ADC0_INPUTCTRL_MUXPOS_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
128#define ADC0_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN2
129#define ADC0_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN3
130#define ADC0_INPUTCTRL_MUXPOS_PA04 ADC_INPUTCTRL_MUXPOS_AIN4
131#define ADC0_INPUTCTRL_MUXPOS_PA05 ADC_INPUTCTRL_MUXPOS_AIN5
132#define ADC0_INPUTCTRL_MUXPOS_PA06 ADC_INPUTCTRL_MUXPOS_AIN6
133#define ADC0_INPUTCTRL_MUXPOS_PA07 ADC_INPUTCTRL_MUXPOS_AIN7
134#define ADC0_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN8
135#define ADC0_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN9
136#define ADC0_INPUTCTRL_MUXPOS_PA10 ADC_INPUTCTRL_MUXPOS_AIN10
137#define ADC0_INPUTCTRL_MUXPOS_PA11 ADC_INPUTCTRL_MUXPOS_AIN11
138#define ADC0_INPUTCTRL_MUXPOS_PB00 ADC_INPUTCTRL_MUXPOS_AIN12
139#define ADC0_INPUTCTRL_MUXPOS_PB01 ADC_INPUTCTRL_MUXPOS_AIN13
140#define ADC0_INPUTCTRL_MUXPOS_PB02 ADC_INPUTCTRL_MUXPOS_AIN14
141#define ADC0_INPUTCTRL_MUXPOS_PB03 ADC_INPUTCTRL_MUXPOS_AIN15
143#define ADC1_INPUTCTRL_MUXPOS_PB08 ADC_INPUTCTRL_MUXPOS_AIN0
144#define ADC1_INPUTCTRL_MUXPOS_PB09 ADC_INPUTCTRL_MUXPOS_AIN1
145#define ADC1_INPUTCTRL_MUXPOS_PA08 ADC_INPUTCTRL_MUXPOS_AIN2
146#define ADC1_INPUTCTRL_MUXPOS_PA09 ADC_INPUTCTRL_MUXPOS_AIN3
147#define ADC1_INPUTCTRL_MUXPOS_PC02 ADC_INPUTCTRL_MUXPOS_AIN4
148#define ADC1_INPUTCTRL_MUXPOS_PC03 ADC_INPUTCTRL_MUXPOS_AIN5
149#define ADC1_INPUTCTRL_MUXPOS_PB04 ADC_INPUTCTRL_MUXPOS_AIN6
150#define ADC1_INPUTCTRL_MUXPOS_PB05 ADC_INPUTCTRL_MUXPOS_AIN7
151#define ADC1_INPUTCTRL_MUXPOS_PB06 ADC_INPUTCTRL_MUXPOS_AIN8
152#define ADC1_INPUTCTRL_MUXPOS_PB07 ADC_INPUTCTRL_MUXPOS_AIN9
153#define ADC1_INPUTCTRL_MUXPOS_PC00 ADC_INPUTCTRL_MUXPOS_AIN10
154#define ADC1_INPUTCTRL_MUXPOS_PC01 ADC_INPUTCTRL_MUXPOS_AIN11
155#define ADC1_INPUTCTRL_MUXPOS_PC30 ADC_INPUTCTRL_MUXPOS_AIN12
156#define ADC1_INPUTCTRL_MUXPOS_PC31 ADC_INPUTCTRL_MUXPOS_AIN13
157#define ADC1_INPUTCTRL_MUXPOS_PD00 ADC_INPUTCTRL_MUXPOS_AIN14
158#define ADC1_INPUTCTRL_MUXPOS_PD01 ADC_INPUTCTRL_MUXPOS_AIN15
160#define ADC0_INPUTCTRL_MUXNEG_PA02 ADC_INPUTCTRL_MUXPOS_AIN0
161#define ADC0_INPUTCTRL_MUXNEG_PA03 ADC_INPUTCTRL_MUXPOS_AIN1
162#define ADC0_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN2
163#define ADC0_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN3
164#define ADC0_INPUTCTRL_MUXNEG_PA04 ADC_INPUTCTRL_MUXPOS_AIN4
165#define ADC0_INPUTCTRL_MUXNEG_PA05 ADC_INPUTCTRL_MUXPOS_AIN5
166#define ADC0_INPUTCTRL_MUXNEG_PA06 ADC_INPUTCTRL_MUXPOS_AIN6
167#define ADC0_INPUTCTRL_MUXNEG_PA07 ADC_INPUTCTRL_MUXPOS_AIN7
169#define ADC1_INPUTCTRL_MUXNEG_PB08 ADC_INPUTCTRL_MUXPOS_AIN0
170#define ADC1_INPUTCTRL_MUXNEG_PB09 ADC_INPUTCTRL_MUXPOS_AIN1
171#define ADC1_INPUTCTRL_MUXNEG_PA08 ADC_INPUTCTRL_MUXPOS_AIN2
172#define ADC1_INPUTCTRL_MUXNEG_PA09 ADC_INPUTCTRL_MUXPOS_AIN3
173#define ADC1_INPUTCTRL_MUXNEG_PC02 ADC_INPUTCTRL_MUXPOS_AIN4
174#define ADC1_INPUTCTRL_MUXNEG_PC03 ADC_INPUTCTRL_MUXPOS_AIN5
175#define ADC1_INPUTCTRL_MUXNEG_PB04 ADC_INPUTCTRL_MUXPOS_AIN6
176#define ADC1_INPUTCTRL_MUXNEG_PB05 ADC_INPUTCTRL_MUXPOS_AIN7
182#define DAC_RES_BITS (12)
183
187#define DAC_NUMOF (2)
188
193#define RTT_MAX_VALUE (0xffffffff)
194#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
195#define RTT_MIN_FREQUENCY (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
196#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
203static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
204 GPIO_PIN(PB, 0), GPIO_PIN(PB, 2), GPIO_PIN(PA, 2),
205 GPIO_PIN(PC, 0), GPIO_PIN(PC, 1)
206};
207
211static const gpio_t gclk_io_pins[] = {
212 GPIO_PIN(PA, 10), GPIO_PIN(PA, 11), GPIO_PIN(PA, 14),
213 GPIO_PIN(PA, 15), GPIO_PIN(PA, 16), GPIO_PIN(PA, 17),
214 GPIO_PIN(PA, 27), GPIO_PIN(PA, 30), GPIO_PIN(PB, 10),
215 GPIO_PIN(PB, 11), GPIO_PIN(PB, 12), GPIO_PIN(PB, 13),
216 GPIO_PIN(PB, 14), GPIO_PIN(PB, 15), GPIO_PIN(PB, 16),
217 GPIO_PIN(PB, 17), GPIO_PIN(PB, 18), GPIO_PIN(PB, 19),
218 GPIO_PIN(PB, 20), GPIO_PIN(PB, 21), GPIO_PIN(PB, 22),
219 GPIO_PIN(PB, 23)
220};
221
226static const uint8_t gclk_io_ids[] = {
227 4, 5, 0, 1, 2, 3, 1, 0, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1
228};
229
235 /* config word 0 */
236 uint32_t bod33_disable : 1;
237 uint32_t bod33_level : 8;
238 uint32_t bod33_action : 2;
239 uint32_t bod33_hysteresis : 4;
240 const uint32_t bod12_calibration : 11;
241 uint32_t nvm_boot_size : 4;
242 uint32_t reserved_0 : 2;
243 /* config word 1 */
244 uint32_t smart_eeprom_blocks : 4;
246 uint32_t ram_eccdis : 1;
247 uint32_t reserved_1 : 8;
248 uint32_t wdt_enable : 1;
249 uint32_t wdt_always_on : 1;
250 uint32_t wdt_period : 4;
251 uint32_t wdt_window : 4;
252 uint32_t wdt_ewoffset : 4;
253 uint32_t wdt_window_enable : 1;
254 uint32_t reserved_2 : 1;
255 /* config word 2 */
256 uint32_t nvm_locks;
257 /* config word 3 */
258 uint32_t user_page;
259 /* config word 4 */
260 uint32_t reserved_3;
261 /* config words 5,6,7 */
262 uint32_t user_pages[3];
263};
264
269#define SAM0_QSPI_PIN_CLK GPIO_PIN(PB, 10)
270#define SAM0_QSPI_PIN_CS GPIO_PIN(PB, 11)
271#define SAM0_QSPI_PIN_DATA_0 GPIO_PIN(PA, 8)
272#define SAM0_QSPI_PIN_DATA_1 GPIO_PIN(PA, 9)
273#define SAM0_QSPI_PIN_DATA_2 GPIO_PIN(PA, 10)
274#define SAM0_QSPI_PIN_DATA_3 GPIO_PIN(PA, 11)
275#define SAM0_QSPI_MUX GPIO_MUX_H
282#define SAM0_SDHC_MUX GPIO_MUX_I
284#define SAM0_SDHC0_PIN_SDCMD GPIO_PIN(PA, 8)
285#define SAM0_SDHC0_PIN_SDDAT0 GPIO_PIN(PA, 9)
286#define SAM0_SDHC0_PIN_SDDAT1 GPIO_PIN(PA, 10)
287#define SAM0_SDHC0_PIN_SDDAT2 GPIO_PIN(PA, 11)
288#define SAM0_SDHC0_PIN_SDDAT3 GPIO_PIN(PB, 10)
289#define SAM0_SDHC0_PIN_SDCK GPIO_PIN(PB, 11)
291#define SAM0_SDHC1_PIN_SDCMD GPIO_PIN(PA, 20)
292#define SAM0_SDHC1_PIN_SDDAT0 GPIO_PIN(PB, 18)
293#define SAM0_SDHC1_PIN_SDDAT1 GPIO_PIN(PB, 19)
294#define SAM0_SDHC1_PIN_SDDAT2 GPIO_PIN(PB, 20)
295#define SAM0_SDHC1_PIN_SDDAT3 GPIO_PIN(PB, 21)
296#define SAM0_SDHC1_PIN_SDCK GPIO_PIN(PA, 21)
299#ifdef __cplusplus
300}
301#endif
302
303#endif /* PERIPH_CPU_H */
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
CPU specific definitions for CAN controllers.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
static const gpio_t sam0_adc_pins[1][20]
Pins that can be used for ADC input.
Definition periph_cpu.h:105
static const uint8_t gclk_io_ids[]
GCLK IDs of pins that have peripheral function GCLK - This maps directly to gclk_io_pins.
Definition periph_cpu.h:226
static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS]
RTC input pins that can be used for tamper detection and wake from Deep Sleep.
Definition periph_cpu.h:203
static const gpio_t gclk_io_pins[]
Pins that have peripheral function GCLK.
Definition periph_cpu.h:211
NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on.
Definition periph_cpu.h:177
uint32_t reserved_3
Factory settings - do not change.
Definition periph_cpu.h:260
uint32_t wdt_enable
WDT Enable at power-on.
Definition periph_cpu.h:248
uint32_t nvm_locks
NVM Region Lock Bits.
Definition periph_cpu.h:256
uint32_t smart_eeprom_page_size
SmartEEPROM Page Size
Definition periph_cpu.h:245
uint32_t user_page
User page
Definition periph_cpu.h:258
uint32_t smart_eeprom_blocks
NVM Blocks per SmartEEPROM sector
Definition periph_cpu.h:244
uint32_t reserved_0
Factory settings - do not change.
Definition periph_cpu.h:242
uint32_t bod33_level
BOD33 threshold level at power-on.
Definition periph_cpu.h:237
uint32_t wdt_window_enable
WDT Window mode enabled on power-on
Definition periph_cpu.h:253
uint32_t wdt_period
WDT Period at power-on.
Definition periph_cpu.h:250
uint32_t bod33_disable
BOD33 Disable at power-on.
Definition periph_cpu.h:236
uint32_t wdt_ewoffset
WDT Early Warning Interrupt Offset
Definition periph_cpu.h:252
uint32_t ram_eccdis
RAM ECC Disable
Definition periph_cpu.h:246
uint32_t reserved_1
Factory settings - do not change.
Definition periph_cpu.h:247
uint32_t user_pages[3]
User pages
Definition periph_cpu.h:262
uint32_t bod33_hysteresis
BOD33 Hysteresis configuration
Definition periph_cpu.h:239
uint32_t reserved_2
Factory settings - do not change.
Definition periph_cpu.h:254
const uint32_t bod12_calibration
Factory settings - do not change.
Definition periph_cpu.h:240
uint32_t bod33_action
BOD33 Action at power-on.
Definition periph_cpu.h:238
uint32_t nvm_boot_size
NVM Bootloader Size
Definition periph_cpu.h:241
uint32_t wdt_always_on
WDT Always-On at power-on.
Definition periph_cpu.h:249
uint32_t wdt_window
WDT Window at power-on.
Definition periph_cpu.h:251
Unit helper macros.