periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 #include "exti_config.h"
26 #include "timer_config.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
35 #define CPUID_LEN (16U)
36 
41 #define PERIPH_SPI_NEEDS_INIT_CS
42 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
43 #ifndef MODULE_PERIPH_DMA
44 #define PERIPH_SPI_NEEDS_TRANSFER_REG
45 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
46 #endif
47 
53 #define PERIPH_I2C_NEED_READ_REG
54 #define PERIPH_I2C_NEED_READ_REGS
55 #define PERIPH_I2C_NEED_WRITE_REG
56 #define PERIPH_I2C_NEED_WRITE_REGS
57 
63 #define HAVE_GPIO_T
64 typedef uint32_t gpio_t;
70 #define GPIO_UNDEF (0xffffffff)
71 
76 #ifdef CPU_FAM_SAML11
77 #define GPIO_PIN(x, y) (((gpio_t)(&PORT_SEC->Group[x])) | y)
78 #else
79 #define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
80 #endif
81 
85 enum {
86  PA = 0,
87  PB = 1,
88  PC = 2,
89  PD = 3,
90 };
91 
100 #define GPIO_MODE(pr, ie, pe) (pr | (ie << 1) | (pe << 2))
101 
102 #ifndef DOXYGEN
103 
106 #define HAVE_GPIO_MODE_T
107 typedef enum {
108  GPIO_IN = GPIO_MODE(0, 1, 0),
109  GPIO_IN_PD = GPIO_MODE(0, 1, 1),
110  GPIO_IN_PU = GPIO_MODE(1, 1, 1),
111  GPIO_OUT = GPIO_MODE(0, 0, 0),
112  GPIO_OD = 0xfe,
113  GPIO_OD_PU = 0xff
114 } gpio_mode_t;
115 
120 #define HAVE_GPIO_FLANK_T
121 typedef enum {
122  GPIO_FALLING = 2,
123  GPIO_RISING = 1,
124  GPIO_BOTH = 3
125 } gpio_flank_t;
127 #endif /* ndef DOXYGEN */
128 
132 #ifndef SAM_MUX_T
133 typedef enum {
134  GPIO_MUX_A = 0x0,
135  GPIO_MUX_B = 0x1,
136  GPIO_MUX_C = 0x2,
137  GPIO_MUX_D = 0x3,
138  GPIO_MUX_E = 0x4,
139  GPIO_MUX_F = 0x5,
140  GPIO_MUX_G = 0x6,
141  GPIO_MUX_H = 0x7,
142 } gpio_mux_t;
143 #endif
144 
148 typedef enum {
153 } uart_rxpad_t;
154 
158 typedef enum {
163 } uart_txpad_t;
164 
168 typedef enum {
174 } uart_flag_t;
175 
176 #ifndef DOXYGEN
177 
184 #define HAVE_UART_DATA_BITS_T
185 typedef enum {
186  UART_DATA_BITS_5 = 0x5,
187  UART_DATA_BITS_6 = 0x6,
188  UART_DATA_BITS_7 = 0x7,
189  UART_DATA_BITS_8 = 0x0,
197 #define uart_pin_rx(dev) uart_config[dev].rx_pin
198 #define uart_pin_tx(dev) uart_config[dev].tx_pin
199 
201 #endif /* ndef DOXYGEN */
202 
203 
207 #ifndef UART_TXBUF_SIZE
208 #define UART_TXBUF_SIZE (64)
209 #endif
210 
224 typedef struct {
225  SercomUsart *dev;
226  gpio_t rx_pin;
227  gpio_t tx_pin;
228 #ifdef MODULE_PERIPH_UART_HW_FC
229  gpio_t rts_pin;
230  gpio_t cts_pin;
231 #endif
236  uint8_t gclk_src;
237 } uart_conf_t;
238 
242 typedef struct {
243 #ifdef REV_TCC
244  Tcc *dev;
245 #endif
246 #ifdef MCLK
247  volatile uint32_t *mclk;
248  uint32_t mclk_mask;
249 #else
250  uint32_t pm_mask;
251 #endif
252  uint16_t gclk_id;
253 } tcc_cfg_t;
254 
258 #ifdef MCLK
259 #define TCC_CONFIG(tim) { \
260  .dev = tim, \
261  .mclk = MCLK_ ## tim, \
262  .mclk_mask = MCLK_ ## tim ## _MASK, \
263  .gclk_id = tim ## _GCLK_ID, }
264 #else
265 #define TCC_CONFIG(tim) { \
266  .dev = tim, \
267  .pm_mask = PM_APBCMASK_ ## tim, \
268  .gclk_id = tim ## _GCLK_ID, }
269 #endif
270 
274 typedef struct {
275  gpio_t pin;
277  uint8_t chan;
279 
283 typedef struct {
286  uint8_t chan_numof;
287  uint8_t gclk_src;
288 } pwm_conf_t;
289 
293 typedef enum {
298 } spi_misopad_t;
299 
303 typedef enum {
308 } spi_mosipad_t;
309 
310 #ifndef DOXYGEN
311 
315 #define HAVE_SPI_MODE_T
316 typedef enum {
317  SPI_MODE_0 = 0x0,
318  SPI_MODE_1 = 0x1,
319  SPI_MODE_2 = 0x2,
320  SPI_MODE_3 = 0x3
321 } spi_mode_t;
328 #define HAVE_SPI_CLK_T
329 typedef enum {
330  SPI_CLK_100KHZ = 100000U,
331  SPI_CLK_400KHZ = 400000U,
332  SPI_CLK_1MHZ = 1000000U,
333  SPI_CLK_5MHZ = 5000000U,
334  SPI_CLK_10MHZ = 10000000U
335 } spi_clk_t;
342 #define spi_pin_mosi(dev) spi_config[dev].mosi_pin
343 #define spi_pin_miso(dev) spi_config[dev].miso_pin
344 #define spi_pin_clk(dev) spi_config[dev].clk_pin
345 
347 #endif /* ndef DOXYGEN */
348 
352 typedef struct {
353  SercomSpi *dev;
354  gpio_t miso_pin;
355  gpio_t mosi_pin;
356  gpio_t clk_pin;
362  uint8_t gclk_src;
363 #ifdef MODULE_PERIPH_DMA
364  uint8_t tx_trigger;
365  uint8_t rx_trigger;
366 #endif
367 } spi_conf_t;
373 typedef enum {
376 } i2c_flag_t;
377 
378 #ifndef DOXYGEN
379 
383 #define HAVE_I2C_SPEED_T
384 typedef enum {
385  I2C_SPEED_LOW = 10000U,
386  I2C_SPEED_NORMAL = 100000U,
387  I2C_SPEED_FAST = 400000U,
388  I2C_SPEED_FAST_PLUS = 1000000U,
389  I2C_SPEED_HIGH = 3400000U,
390 } i2c_speed_t;
397 #define i2c_pin_sda(dev) i2c_config[dev].sda_pin
398 #define i2c_pin_scl(dev) i2c_config[dev].scl_pin
399 
401 #endif /* ndef DOXYGEN */
402 
415 typedef struct {
416  SercomI2cm *dev;
417  i2c_speed_t speed;
418  gpio_t scl_pin;
419  gpio_t sda_pin;
421  uint8_t gclk_src;
422  uint8_t flags;
423 } i2c_conf_t;
424 
428 typedef struct {
429  Tc *dev;
431 #ifdef MCLK
432  volatile uint32_t *mclk;
433  uint32_t mclk_mask;
434  uint16_t gclk_id;
435 #else
436  uint32_t pm_mask;
437  uint16_t gclk_ctrl;
438 #endif
439  uint8_t gclk_src;
440  uint16_t flags;
441 } tc32_conf_t;
442 
446 #define TIMER_CHANNEL_NUMOF (2)
447 
454 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
455 
461 void gpio_pm_cb_enter(int deep);
462 
468 void gpio_pm_cb_leave(int deep);
469 
475 void cpu_pm_cb_enter(int deep);
476 
482 void cpu_pm_cb_leave(int deep);
483 
489 static inline void sam0_cortexm_sleep(int deep)
490 {
491 #ifdef MODULE_PERIPH_GPIO
492  gpio_pm_cb_enter(deep);
493 #endif
494 
495  cpu_pm_cb_enter(deep);
496 
497  cortexm_sleep(deep);
498 
499  cpu_pm_cb_leave(deep);
500 
501 #ifdef MODULE_PERIPH_GPIO
502  gpio_pm_cb_leave(deep);
503 #endif
504 }
505 
511 void gpio_disable_mux(gpio_t pin);
512 
516 typedef enum {
517  SAM0_VREG_LDO, /*< LDO, always available but not very power efficient */
518  SAM0_VREG_BUCK /*< Buck converter, efficient but may clash with internal
519  fast clock generators (see errata sheets) */
520 } sam0_supc_t;
521 
535 static inline void sam0_set_voltage_regulator(sam0_supc_t src)
536 {
537 #ifdef REG_SUPC_VREG
538  SUPC->VREG.bit.SEL = src;
539  while (!SUPC->STATUS.bit.VREGRDY) {}
540 #else
541  (void) src;
542  assert(0);
543 #endif
544 }
545 
553 uint32_t sam0_gclk_freq(uint8_t id);
554 
560 void sam0_gclk_enable(uint8_t id);
561 
569 static inline uint8_t sercom_id(const void *sercom)
570 {
571 #ifdef SERCOM0
572  if (sercom == SERCOM0) {
573  return 0;
574  }
575 #endif
576 #ifdef SERCOM1
577  if (sercom == SERCOM1) {
578  return 1;
579  }
580 #endif
581 #ifdef SERCOM2
582  if (sercom == SERCOM2) {
583  return 2;
584  }
585 #endif
586 #ifdef SERCOM3
587  if (sercom == SERCOM3) {
588  return 3;
589  }
590 #endif
591 #ifdef SERCOM4
592  if (sercom == SERCOM4) {
593  return 4;
594  }
595 #endif
596 #ifdef SERCOM5
597  if (sercom == SERCOM5) {
598  return 5;
599  }
600 #endif
601 #ifdef SERCOM6
602  if (sercom == SERCOM6) {
603  return 6;
604  }
605 #endif
606 #ifdef SERCOM7
607  if (sercom == SERCOM7) {
608  return 7;
609  }
610 #endif
611 
612  /* should not be reached, so fail with assert */
613  assert(false);
614 
615  return SERCOM_INST_NUM;
616 }
617 
623 static inline void sercom_clk_en(void *sercom)
624 {
625  const uint8_t id = sercom_id(sercom);
626 #if defined(CPU_FAM_SAMD21)
627  PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
628 #elif defined (CPU_FAM_SAMD5X)
629  if (id < 2) {
630  MCLK->APBAMASK.reg |= (1 << (id + 12));
631  } else if (id < 4) {
632  MCLK->APBBMASK.reg |= (1 << (id + 7));
633  } else {
634  MCLK->APBDMASK.reg |= (1 << (id - 4));
635  }
636 #else
637  if (id < 5) {
638  MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
639  }
640 #if defined(CPU_FAM_SAML21)
641  else {
642  MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
643  }
644 #endif /* CPU_FAM_SAML21 */
645 #endif
646 }
647 
653 static inline void sercom_clk_dis(void *sercom)
654 {
655  const uint8_t id = sercom_id(sercom);
656 #if defined(CPU_FAM_SAMD21)
657  PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
658 #elif defined (CPU_FAM_SAMD5X)
659  if (id < 2) {
660  MCLK->APBAMASK.reg &= ~(1 << (id + 12));
661  } else if (id < 4) {
662  MCLK->APBBMASK.reg &= ~(1 << (id + 7));
663  } else {
664  MCLK->APBDMASK.reg &= ~(1 << (id - 4));
665  }
666 #else
667  if (id < 5) {
668  MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
669  }
670 #if defined (CPU_FAM_SAML21)
671  else {
672  MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
673  }
674 #endif /* CPU_FAM_SAML21 */
675 #endif
676 }
677 
678 #ifdef CPU_FAM_SAMD5X
679 static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
680  if (sercom_id < 2)
681  return sercom_id + 7;
682  if (sercom_id < 4)
683  return sercom_id + 21;
684  else
685  return sercom_id + 30;
686 }
687 #endif
688 
695 static inline void sercom_set_gen(void *sercom, uint8_t gclk)
696 {
697  const uint8_t id = sercom_id(sercom);
698  sam0_gclk_enable(gclk);
699 #if defined(CPU_FAM_SAMD21)
700  GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
701  (SERCOM0_GCLK_ID_CORE + id));
702  while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
703 #elif defined(CPU_FAM_SAMD5X)
704  GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
705 #else
706  if (id < 5) {
707  GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
708  }
709 #if defined(CPU_FAM_SAML21)
710  else {
711  GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
712  }
713 #endif /* CPU_FAM_SAML21 */
714 #endif
715 }
716 
720 static inline bool cpu_woke_from_backup(void)
721 {
722 #ifdef RSTC_RCAUSE_BACKUP
723  return RSTC->RCAUSE.bit.BACKUP;
724 #else
725  return false;
726 #endif
727 }
728 
732 typedef struct {
733  gpio_t pin;
734  uint32_t muxpos;
736 
740 #if defined(USB_INST_NUM) || defined(DOXYGEN)
741 typedef struct {
742  gpio_t dm;
743  gpio_t dp;
745  UsbDevice *device;
746  uint8_t gclk_src;
748 #endif /* USB_INST_NUM */
749 
754 /* Limits are in clock cycles according to data sheet.
755  As the WDT is clocked by a 1024 Hz clock, 1 cycle ≈ 1 ms */
756 #define NWDT_TIME_LOWER_LIMIT (8U)
757 #define NWDT_TIME_UPPER_LIMIT (16384U)
758 
764 #define WDT_HAS_STOP (1)
765 
768 #define WDT_HAS_INIT (1)
769 
819 #define DMA_TRIGGER_DISABLED 0
820 
824 #if defined(CPU_FAM_SAML21) || defined(DOXYGEN)
825 #define DMA_DESCRIPTOR_IN_LPSRAM
826 #endif
827 
831 #ifdef DMA_DESCRIPTOR_IN_LPSRAM
832 #define DMA_DESCRIPTOR_ATTRS __attribute__((section(".backup.bss")))
833 #else
834 #define DMA_DESCRIPTOR_ATTRS
835 #endif
836 
840 typedef unsigned dma_t;
841 
845 typedef enum {
850 } dma_incr_t;
851 
855 void dma_init(void);
856 
867 dma_t dma_acquire_channel(void);
868 
874 void dma_release_channel(dma_t dma);
875 
884 void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq);
885 
899 void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst,
900  size_t num, dma_incr_t incr);
901 
922 void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr);
923 
944 void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr);
945 
965 void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width,
966  const void *src, void *dst, size_t num, dma_incr_t incr);
967 
986 void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src,
987  size_t num, bool incr);
988 
1007 void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num,
1008  bool incr);
1009 
1015 void dma_start(dma_t dma);
1016 
1026 void dma_wait(dma_t dma);
1027 
1036 void dma_cancel(dma_t dma);
1039 #ifdef __cplusplus
1040 }
1041 #endif
1042 
1043 #endif /* PERIPH_CPU_COMMON_H */
1044 
select peripheral function D
port A
fast mode: ~400 kbit/s
Definition: i2c.h:184
CPOL=0, CPHA=1.
Definition: spi.h:159
uint32_t sam0_gclk_freq(uint8_t id)
Returns the frequency of a GCLK provider.
configure as output in push-pull mode
Definition: gpio.h:117
unsigned dma_t
DMA channel type.
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:141
high speed mode: ~3400 kbit/s
Definition: i2c.h:186
dma_incr_t
Available DMA address increment modes.
I2C configuration options.
Definition: periph_cpu.h:128
void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying source and block si...
Tc * dev
pointer to the used Timer device
use pad 0 for MISO line
emit interrupt on rising flank
Definition: gpio.h:131
static void sam0_cortexm_sleep(int deep)
Wrapper for cortexm_sleep calling power management callbacks.
uart_flag_t
Available SERCOM UART flag selections.
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
select peripheral function E
gpio_mux_t clk_mux
alternate function for CLK pin (mux)
i2c_flag_t
Available SERCOM I2C flag selections.
select peripheral function B
No flags set.
select pad 3
const pwm_conf_chan_t * chan
channel configuration
spi_misopad_t
Available values for SERCOM SPI MISO pad selection.
Common configuration for timer devices.
uint8_t gclk_src
GCLK source which clocks TIMER.
void gpio_pm_cb_enter(int deep)
Called before the power management enters a power mode.
SercomSpi * dev
pointer to the used SPI device
void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying destination and blo...
void gpio_pm_cb_leave(int deep)
Called after the power management left a power mode.
run SERCOM in standby mode
enum IRQn IRQn_Type
Interrupt Number Definition.
uart_txpad_t
Available values for SERCOM UART TX pad selection.
uint8_t gclk_src
GCLK source which supplys SERCOM.
CPOL=0, CPHA=0.
Definition: spi.h:158
uint8_t gclk_src
GCLK source which supplys SERCOM.
gpio_mux_t mux
pin function multiplex value
select pad 1
select pad 0
void cpu_pm_cb_enter(int deep)
Called before the power management enters a power mode.
select peripheral function F
port B
static void sam0_set_voltage_regulator(sam0_supc_t src)
Switch the internal voltage regulator used for generating the internal MCU voltages.
Increment both addresses after a beat.
void dma_cancel(dma_t dma)
Cancel an active DMA transfer.
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:181
drive the SPI bus with 100KHz
Definition: spi.h:174
uint16_t flags
flags for CTRA, e.g.
Don&#39;t increment any addresses after a beat.
invert RX signal
spi_mosipad_t mosi_pad
pad to use for MOSI and CLK line
drive the SPI bus with 400KHz
Definition: spi.h:175
gpio_t dm
D- line gpio.
No flags set.
invert TX signal
void dma_release_channel(dma_t dma)
Release a previously acquired DMA channel.
ADC Channel Configuration.
PWM device configuration.
Increment the source address after a beat.
uint8_t gclk_src
GCLK source which supplys 48 MHz.
use pad 0 for MISO line
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
SercomUsart * dev
pointer to the used UART device
emit interrupt on both flanks
Definition: gpio.h:132
select peripheral function H
5 data bits
Definition: uart.h:142
uart_txpad_t tx_pad
pad selection for TX line
uint8_t chan_numof
number of channels
void dma_init(void)
Initialize DMA.
select peripheral function C
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
static void sercom_set_gen(void *sercom, uint8_t gclk)
Configure generator clock for given SERCOM device.
gpio_mux_t mosi_mux
alternate function for MOSI pin (mux)
void dma_start(dma_t dma)
Start a DMA transfer.
select pad 2
uint32_t muxpos
ADC channel pin multiplexer value.
spi_misopad_t miso_pad
pad to use for MISO line
select peripheral function G
void sam0_gclk_enable(uint8_t id)
Enables an on-demand GCLK that has been configured in cpu.c.
gpio_t pin
GPIO pin.
select peripheral function A
select pad 2
USB peripheral parameters.
static uint8_t sercom_id(const void *sercom)
Return the numeric id of a SERCOM device derived from its address.
#define assert(cond)
abort the program if assertion is false
Definition: assert.h:104
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
7 data bits
Definition: uart.h:144
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
CPOL=1, CPHA=1.
Definition: spi.h:161
uart_rxpad_t
Available values for SERCOM UART RX pad selection.
gpio_mux_t miso_mux
alternate function for MISO pin (mux)
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
IRQn_Type irq
IRQ# of Timer Interrupt.
void gpio_disable_mux(gpio_t pin)
Disable alternate function (PMUX setting) for a PORT pin.
uint16_t gclk_ctrl
GCLK_CLKCTRL_ID for the Timer.
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
gpio_t clk_pin
used CLK pin
drive the SPI bus with 5MHz
Definition: spi.h:177
static void sercom_clk_en(void *sercom)
Enable peripheral clock for given SERCOM device.
uart_rxpad_t rx_pad
pad selection for RX line
port C
SercomI2cm * dev
pointer to the used I2C device
drive the SPI bus with 10MHz
Definition: spi.h:178
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
void cpu_pm_cb_leave(int deep)
Called after the power management left a power mode.
emit interrupt on falling flank
Definition: gpio.h:130
run SERCOM in standby mode
gpio_t pin
ADC channel pin.
drive the SPI bus with 1MHz
Definition: spi.h:176
8 data bits
Definition: uart.h:145
uint16_t gclk_id
TCn_GCLK_ID.
Increment destination address after a beat.
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
PWM channel configuration data structure.
6 data bits
Definition: uart.h:143
configure as input with pull-up resistor
Definition: gpio.h:116
dma_t dma_acquire_channel(void)
Acquire a DMA channel.
use pad 0 for RX line
use pad 0 for MISO line
use pad 3 for MOSI, pad 1 for SCK
use pad 0 for MOSI, pad 3 for SCK
uint8_t flags
allow SERCOM to run in standby mode
static bool cpu_woke_from_backup(void)
Returns true if the CPU woke deep sleep (backup/standby)
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
gpio_mux_t mux
alternate function (mux)
static void cortexm_sleep(int deep)
Put the CPU into (deep) sleep mode, using the WFI instruction.
Definition: cpu.h:160
spi_mosipad_t
Available values for SERCOM SPI MOSI and SCK pad selection.
use pad 2 for MOSI, pad 3 for SCK
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
low speed mode: ~10 kbit/s
Definition: i2c.h:182
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
sam0_supc_t
Available voltage regulators on the supply controller.
CPOL=1, CPHA=0.
Definition: spi.h:160
uart_flag_t flags
set optional SERCOM flags
SPI configuration structure type.
Definition: periph_cpu.h:273
gpio_mux_t mux
alternative function for pins
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
normal mode: ~100 kbit/s
Definition: i2c.h:183
use pad 0 for MOSI, pad 1 for SCK
configure as input with pull-down resistor
Definition: gpio.h:115
uint8_t chan
TCC channel to use.
tcc_cfg_t tim
timer configuration
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
use pad 0 for MISO line
#define GPIO_MODE(pr, ie, pe)
Generate GPIO mode bitfields.
UsbDevice * device
ptr to the device registers
void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Append a second transfer descriptor after the default channel descriptor.
gpio_mux_t d_mux
alternate function (mux) for data pins
void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr)
Prepare a transfer without modifying the source address settings.
gpio_t dp
D+ line gpio.
static void sercom_clk_dis(void *sercom)
Disable peripheral clock for given SERCOM device.
uint8_t gclk_src
GCLK source which supplys SERCOM.
wake from sleep on receive
Timer device configuration.
uint8_t gclk_src
GCLK source which supplys Timer.
void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr)
Prepare a transfer without modifying the destination address settings.
fast plus mode: ~1000 kbit/s
Definition: i2c.h:185
port D