sam0_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_COMMON_H
20 #define PERIPH_CPU_COMMON_H
21 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 #define CPUID_LEN (16U)
32 
37 #define PERIPH_SPI_NEEDS_INIT_CS
38 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
39 #define PERIPH_SPI_NEEDS_TRANSFER_REG
40 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
41 
47 #define HAVE_GPIO_T
48 typedef uint32_t gpio_t;
54 #define GPIO_UNDEF (0xffffffff)
55 
60 #define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
61 
66 #define PM_NUM_MODES (3)
67 
68 #define PM_BLOCKER_INITIAL { .val_u32 = 0x01010101 }
69 
71 #ifndef DOXYGEN
72 
76 #define HAVE_GPIO_FLANK_T
77 typedef enum {
78  GPIO_FALLING = 2,
79  GPIO_RISING = 1,
80  GPIO_BOTH = 3
81 } gpio_flank_t;
83 #endif /* ndef DOXYGEN */
84 
88 typedef enum {
89  GPIO_MUX_A = 0x0,
90  GPIO_MUX_B = 0x1,
91  GPIO_MUX_C = 0x2,
92  GPIO_MUX_D = 0x3,
93  GPIO_MUX_E = 0x4,
94  GPIO_MUX_F = 0x5,
95  GPIO_MUX_G = 0x6,
96  GPIO_MUX_H = 0x7,
97 } gpio_mux_t;
98 
102 typedef enum {
107 } uart_rxpad_t;
108 
112 typedef enum {
117 } uart_txpad_t;
118 
122 typedef enum {
127 } spi_misopad_t;
128 
132 typedef enum {
137 } spi_mosipad_t;
138 
143 #define HAVE_SPI_MODE_T
144 typedef enum {
145  SPI_MODE_0 = 0x0,
146  SPI_MODE_1 = 0x1,
147  SPI_MODE_2 = 0x2,
148  SPI_MODE_3 = 0x3
149 } spi_mode_t;
156 #define HAVE_SPI_CLK_T
157 typedef enum {
158  SPI_CLK_100KHZ = 100000U,
159  SPI_CLK_400KHZ = 400000U,
160  SPI_CLK_1MHZ = 1000000U,
161  SPI_CLK_5MHZ = 5000000U,
162  SPI_CLK_10MHZ = 10000000U
163 } spi_clk_t;
169 typedef struct {
170  SercomSpi *dev;
171  gpio_t miso_pin;
172  gpio_t mosi_pin;
173  gpio_t clk_pin;
179 } spi_conf_t;
180 
187 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
188 
196 static inline int sercom_id(void *sercom)
197 {
198 #if defined(CPU_FAM_SAMD21)
199  return ((((uint32_t)sercom) >> 10) & 0x7) - 2;
200 #elif defined(CPU_FAM_SAML21)
201  return ((((uint32_t)sercom) >> 10) & 0x7);
202 #endif
203 }
204 
208 typedef struct {
209  gpio_t pin;
210  uint32_t muxpos;
212 
213 
214 #ifdef __cplusplus
215 }
216 #endif
217 
218 #endif /* PERIPH_CPU_COMMON_H */
219 
select peripheral function D
static int sercom_id(void *sercom)
Return the numeric id of a SERCOM device derived from its address.
emit interrupt on rising flank
Definition: gpio.h:114
select peripheral function E
gpio_mux_t clk_mux
alternate function for CLK pin (mux)
select peripheral function B
spi_misopad_t
Available values for SERCOM SPI MISO pad selection.
SercomSpi * dev
pointer to the used SPI device
uart_txpad_t
Available values for SERCOM UART TX pad selection.
select peripheral function F
drive the SPI bus with 100KHz
spi_mosipad_t mosi_pad
pad to use for MOSI and CLK line
drive the SPI bus with 400KHz
ADC Channel Configuration.
emit interrupt on both flanks
Definition: gpio.h:115
select peripheral function H
select peripheral function C
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
gpio_mux_t mosi_mux
alternate function for MOSI pin (mux)
uint32_t muxpos
ADC channel pin multiplexer value.
spi_misopad_t miso_pad
pad to use for MISO line
select peripheral function G
select peripheral function A
uart_rxpad_t
Available values for SERCOM UART RX pad selection.
gpio_mux_t miso_mux
alternate function for MISO pin (mux)
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
drive the SPI bus with 5MHz
drive the SPI bus with 10MHz
emit interrupt on falling flank
Definition: gpio.h:113
drive the SPI bus with 1MHz
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
use pad 3 for MOSI, pad 1 for SCK
use pad 0 for MOSI, pad 3 for SCK
spi_mosipad_t
Available values for SERCOM SPI MOSI and SCK pad selection.
use pad 2 for MOSI, pad 3 for SCK
SPI configuration data structure.
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
use pad 0 for MOSI, pad 1 for SCK