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periph_cpu_common.h
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1/*
2 * Copyright (C) 2016 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
21#ifndef PERIPH_CPU_COMMON_H
22#define PERIPH_CPU_COMMON_H
23
24#include "cpu.h"
25#include "exti_config.h"
26#include "timer_config.h"
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
35#define CPUID_LEN (16U)
36
41#define PERIPH_SPI_NEEDS_INIT_CS
42#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
43#ifndef MODULE_PERIPH_DMA
44#define PERIPH_SPI_NEEDS_TRANSFER_REG
45#define PERIPH_SPI_NEEDS_TRANSFER_REGS
46#endif
53#define PERIPH_I2C_NEED_READ_REG
54#define PERIPH_I2C_NEED_READ_REGS
55#define PERIPH_I2C_NEED_WRITE_REG
56#define PERIPH_I2C_NEED_WRITE_REGS
62#define PERIPH_I2C_MAX_BYTES_PER_FRAME 256
63
68#define HAVE_GPIO_T
69typedef uint32_t gpio_t;
75#define GPIO_UNDEF (0xffffffff)
76
81#ifdef MODULE_PERIPH_GPIO_FAST_READ
82#ifdef PORT_IOBUS_SEC
83#define GPIO_PIN(x, y) (((gpio_t)(&PORT_IOBUS_SEC->Group[x])) | y)
84#else /* Use IOBUS access when available */
85#define GPIO_PIN(x, y) (((gpio_t)(&PORT_IOBUS->Group[x])) | y)
86#endif /* PORT_IOBUS_SEC */
87#else
88#ifdef PORT_SEC
89#define GPIO_PIN(x, y) (((gpio_t)(&PORT_SEC->Group[x])) | y)
90#else
91#define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
92#endif /* PORT_IOBUS_SEC */
93#endif
94
98enum {
99 PA = 0,
100 PB = 1,
101 PC = 2,
102 PD = 3,
103};
104
113#define GPIO_MODE(pr, ie, pe) (pr | (ie << 1) | (pe << 2))
114
115#ifndef DOXYGEN
119#define HAVE_GPIO_MODE_T
120typedef enum {
121 GPIO_IN = GPIO_MODE(0, 1, 0),
122 GPIO_IN_PD = GPIO_MODE(0, 1, 1),
123 GPIO_IN_PU = GPIO_MODE(1, 1, 1),
124 GPIO_OUT = GPIO_MODE(0, 0, 0),
125 GPIO_OD = 0xfe,
126 GPIO_OD_PU = 0xff
128
129#define HAVE_GPIO_SLEW_T
130typedef enum {
132 GPIO_SLEW_SLOW = 0,
133 GPIO_SLEW_FAST = 0,
136
137#define HAVE_GPIO_PULL_STRENGTH_T
138typedef enum {
140 GPIO_PULL_WEAK = 0,
144
145#define HAVE_GPIO_DRIVE_STRENGTH_T
146typedef enum {
148 GPIO_DRIVE_WEAK = 0,
152
153#define HAVE_GPIO_PULL_T
154typedef enum {
160
161#define HAVE_GPIO_STATE_T
162typedef enum {
170
171#define HAVE_GPIO_IRQ_TRIG_T
172typedef enum {
173 GPIO_TRIGGER_EDGE_RISING = EIC_CONFIG_SENSE0_RISE_Val,
174 GPIO_TRIGGER_EDGE_FALLING = EIC_CONFIG_SENSE0_FALL_Val,
175 GPIO_TRIGGER_EDGE_BOTH = EIC_CONFIG_SENSE0_BOTH_Val,
176 GPIO_TRIGGER_LEVEL_HIGH = EIC_CONFIG_SENSE0_HIGH_Val,
177 GPIO_TRIGGER_LEVEL_LOW = EIC_CONFIG_SENSE0_LOW_Val,
179
180#define HAVE_GPIO_CONF_T
181typedef union gpio_conf_sam0 gpio_conf_t;
182
187#define HAVE_GPIO_FLANK_T
188typedef enum {
189 GPIO_FALLING = 2,
190 GPIO_RISING = 1,
191 GPIO_BOTH = 3
194#endif /* ndef DOXYGEN */
195
201 uint8_t bits;
202 struct {
235 uint8_t : 1; /*< padding */
236 };
237};
238
242#ifndef SAM_MUX_T
260#endif
261
271
275typedef enum {
281
291
292#ifndef DOXYGEN
300#define HAVE_UART_DATA_BITS_T
301typedef enum {
302 UART_DATA_BITS_5 = 0x5,
303 UART_DATA_BITS_6 = 0x6,
304 UART_DATA_BITS_7 = 0x7,
305 UART_DATA_BITS_8 = 0x0,
313#define uart_pin_rx(dev) uart_config[dev].rx_pin
314#define uart_pin_tx(dev) uart_config[dev].tx_pin
317#endif /* ndef DOXYGEN */
318
322#ifndef UART_TXBUF_SIZE
323#define UART_TXBUF_SIZE (64)
324#endif
325
339typedef struct {
340 SercomUsart *dev;
341 gpio_t rx_pin;
342 gpio_t tx_pin;
343#ifdef MODULE_PERIPH_UART_HW_FC
344 gpio_t rts_pin;
345 gpio_t cts_pin;
346#endif
351 uint8_t gclk_src;
353
354enum {
357};
358
362typedef struct {
363 union {
364#ifdef REV_TC
365 Tc *tc;
366#endif
367#ifdef REV_TCC
368 Tcc *tcc;
369#endif
370 } dev;
371#ifdef MCLK
372 volatile uint32_t *mclk;
373 uint32_t mclk_mask;
374#else
375 uint32_t pm_mask;
376#endif
377 uint16_t gclk_id;
378 uint8_t type;
380
384#ifdef MCLK
385#define TC_CONFIG(tim) { \
386 .dev = {.tc = tim}, \
387 .mclk = MCLK_ ## tim, \
388 .mclk_mask = MCLK_ ## tim ## _MASK, \
389 .gclk_id = tim ## _GCLK_ID, \
390 .type = TIMER_TYPE_TC, }
391#else
392#define TC_CONFIG(tim) { \
393 .dev = {.tc = tim}, \
394 .pm_mask = PM_APBCMASK_ ## tim, \
395 .gclk_id = tim ## _GCLK_ID, \
396 .type = TIMER_TYPE_TC, }
397#endif
398
402#ifdef MCLK
403#define TCC_CONFIG(tim) { \
404 .dev = {.tcc = tim}, \
405 .mclk = MCLK_ ## tim, \
406 .mclk_mask = MCLK_ ## tim ## _MASK, \
407 .gclk_id = tim ## _GCLK_ID, \
408 .type = TIMER_TYPE_TCC, }
409#else
410#define TCC_CONFIG(tim) { \
411 .dev = {.tcc = tim}, \
412 .pm_mask = PM_APBCMASK_ ## tim, \
413 .gclk_id = tim ## _GCLK_ID, \
414 .type = TIMER_TYPE_TCC, }
415#endif
416
420typedef struct {
421 gpio_t pin;
423 uint8_t chan;
425
429typedef struct {
432 uint8_t chan_numof;
433 uint8_t gclk_src;
434} pwm_conf_t;
435
445
455
456#ifndef DOXYGEN
461#define HAVE_SPI_MODE_T
462typedef enum {
463 SPI_MODE_0 = 0x0,
464 SPI_MODE_1 = 0x1,
465 SPI_MODE_2 = 0x2,
466 SPI_MODE_3 = 0x3
467} spi_mode_t;
474#define HAVE_SPI_CLK_T
475typedef enum {
476 SPI_CLK_100KHZ = 100000U,
477 SPI_CLK_400KHZ = 400000U,
478 SPI_CLK_1MHZ = 1000000U,
479 SPI_CLK_5MHZ = 5000000U,
480 SPI_CLK_10MHZ = 10000000U
481} spi_clk_t;
488#define spi_pin_mosi(dev) spi_config[dev].mosi_pin
489#define spi_pin_miso(dev) spi_config[dev].miso_pin
490#define spi_pin_clk(dev) spi_config[dev].clk_pin
493#endif /* ndef DOXYGEN */
494
498typedef struct {
499 void *dev;
500 gpio_t miso_pin;
501 gpio_t mosi_pin;
502 gpio_t clk_pin;
508 uint8_t gclk_src;
509#ifdef MODULE_PERIPH_DMA
510 uint8_t tx_trigger;
511 uint8_t rx_trigger;
512#endif
513} spi_conf_t;
519typedef enum {
522} i2c_flag_t;
523
524#ifndef DOXYGEN
529#define HAVE_I2C_SPEED_T
530typedef enum {
531 I2C_SPEED_LOW = 10000U,
532 I2C_SPEED_NORMAL = 100000U,
533 I2C_SPEED_FAST = 400000U,
534 I2C_SPEED_FAST_PLUS = 1000000U,
535 I2C_SPEED_HIGH = 3400000U,
543#define i2c_pin_sda(dev) i2c_config[dev].sda_pin
544#define i2c_pin_scl(dev) i2c_config[dev].scl_pin
547#endif /* ndef DOXYGEN */
548
561typedef struct {
562 SercomI2cm *dev;
563 i2c_speed_t speed;
564 gpio_t scl_pin;
565 gpio_t sda_pin;
567 uint8_t gclk_src;
568 uint8_t flags;
569} i2c_conf_t;
570
574typedef struct {
575 Tc *dev;
577#ifdef MCLK
578 volatile uint32_t *mclk;
579 uint32_t mclk_mask;
580 uint16_t gclk_id;
581#else
582 uint32_t pm_mask;
583 uint16_t gclk_ctrl;
584#endif
585 uint8_t gclk_src;
586 uint16_t flags;
588
592#define TIMER_CHANNEL_NUMOF (2)
593
600void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
601
607void gpio_pm_cb_enter(int deep);
608
614void gpio_pm_cb_leave(int deep);
615
621void cpu_pm_cb_enter(int deep);
622
628void cpu_pm_cb_leave(int deep);
629
635static inline void sam0_cortexm_sleep(int deep)
636{
637#ifdef MODULE_PERIPH_GPIO
638 gpio_pm_cb_enter(deep);
639#endif
640
641 cpu_pm_cb_enter(deep);
642
643 cortexm_sleep(deep);
644
645 cpu_pm_cb_leave(deep);
646
647#ifdef MODULE_PERIPH_GPIO
648 gpio_pm_cb_leave(deep);
649#endif
650}
651
657void gpio_disable_mux(gpio_t pin);
658
662typedef enum {
663 SAM0_VREG_LDO, /*< LDO, always available but not very power efficient */
664 SAM0_VREG_BUCK /*< Buck converter, efficient but may clash with internal
665 fast clock generators (see errata sheets) */
667
682{
683#ifdef REG_SUPC_VREG
684 SUPC->VREG.bit.SEL = src;
685 while (!SUPC->STATUS.bit.VREGRDY) {}
686#else
687 (void) src;
688 assert(0);
689#endif
690}
691
699uint32_t sam0_gclk_freq(uint8_t id);
700
706void sam0_gclk_enable(uint8_t id);
707
715static inline uint8_t sercom_id(const void *sercom)
716{
717#ifdef SERCOM0
718 if (sercom == SERCOM0) {
719 return 0;
720 }
721#endif
722#ifdef SERCOM1
723 if (sercom == SERCOM1) {
724 return 1;
725 }
726#endif
727#ifdef SERCOM2
728 if (sercom == SERCOM2) {
729 return 2;
730 }
731#endif
732#ifdef SERCOM3
733 if (sercom == SERCOM3) {
734 return 3;
735 }
736#endif
737#ifdef SERCOM4
738 if (sercom == SERCOM4) {
739 return 4;
740 }
741#endif
742#ifdef SERCOM5
743 if (sercom == SERCOM5) {
744 return 5;
745 }
746#endif
747#ifdef SERCOM6
748 if (sercom == SERCOM6) {
749 return 6;
750 }
751#endif
752#ifdef SERCOM7
753 if (sercom == SERCOM7) {
754 return 7;
755 }
756#endif
757
758 /* should not be reached, so fail with assert */
759 assert(false);
760
761 return SERCOM_INST_NUM;
762}
763
769static inline void sercom_clk_en(void *sercom)
770{
771 const uint8_t id = sercom_id(sercom);
772#if defined(CPU_COMMON_SAMD21)
773 PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
774#elif defined (CPU_COMMON_SAMD5X)
775 if (id < 2) {
776 MCLK->APBAMASK.reg |= (1 << (id + 12));
777 } else if (id < 4) {
778 MCLK->APBBMASK.reg |= (1 << (id + 7));
779 } else {
780 MCLK->APBDMASK.reg |= (1 << (id - 4));
781 }
782#else
783 if (id < 5) {
784 MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
785 }
786#if defined(CPU_COMMON_SAML21)
787 else {
788 MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
789 }
790#endif /* CPU_COMMON_SAML21 */
791#endif
792}
793
799static inline void sercom_clk_dis(void *sercom)
800{
801 const uint8_t id = sercom_id(sercom);
802#if defined(CPU_COMMON_SAMD21)
803 PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
804#elif defined (CPU_COMMON_SAMD5X)
805 if (id < 2) {
806 MCLK->APBAMASK.reg &= ~(1 << (id + 12));
807 } else if (id < 4) {
808 MCLK->APBBMASK.reg &= ~(1 << (id + 7));
809 } else {
810 MCLK->APBDMASK.reg &= ~(1 << (id - 4));
811 }
812#else
813 if (id < 5) {
814 MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
815 }
816#if defined (CPU_COMMON_SAML21)
817 else {
818 MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
819 }
820#endif /* CPU_COMMON_SAML21 */
821#endif
822}
823
824#ifdef CPU_COMMON_SAMD5X
825static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
826 if (sercom_id < 2) {
827 return sercom_id + 7;
828 } else if (sercom_id < 4) {
829 return sercom_id + 21;
830 } else {
831 return sercom_id + 30;
832 }
833}
834#endif
835
842static inline void sercom_set_gen(void *sercom, uint8_t gclk)
843{
844 const uint8_t id = sercom_id(sercom);
845 sam0_gclk_enable(gclk);
846#if defined(CPU_COMMON_SAMD21)
847 GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
848 (SERCOM0_GCLK_ID_CORE + id));
849 while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
850#elif defined(CPU_COMMON_SAMD5X)
851 GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
852#else
853 if (id < 5) {
854 GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
855 }
856#if defined(CPU_COMMON_SAML21)
857 else {
858 GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
859 }
860#endif /* CPU_COMMON_SAML21 */
861#endif
862}
863
867static inline bool cpu_woke_from_backup(void)
868{
869#ifdef RSTC_RCAUSE_BACKUP
870 return RSTC->RCAUSE.bit.BACKUP;
871#else
872 return false;
873#endif
874}
875
879typedef struct {
880 union {
881 uint32_t inputctrl;
882 uint32_t muxpos;
884 };
885#ifdef ADC0
886 Adc *dev;
887#endif
889
894#ifndef ADC_INPUTCTRL_DIFFMODE
895#define ADC_INPUTCTRL_DIFFMODE (1 << 7)
896#endif
897
901#define ADC_REFSEL_AREFA_PIN GPIO_PIN(PA, 3)
902
906#define ADC_REFSEL_AREFB_PIN GPIO_PIN(PA, 4)
907
908#if defined(ADC_REFCTRL_REFSEL_AREFC) || DOXYGEN
912#define ADC_REFSEL_AREFC_PIN GPIO_PIN(PA, 6)
913#endif
914
915#ifndef DOXYGEN
916#define HAVE_ADC_RES_T
917typedef enum {
918 ADC_RES_6BIT = 0xff,
919#if defined(ADC_CTRLB_RESSEL)
920 ADC_RES_8BIT = ADC_CTRLB_RESSEL_8BIT_Val,
921 ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT_Val,
922 ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT_Val,
923#elif defined(ADC_CTRLC_RESSEL)
924 ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT_Val,
925 ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT_Val,
926 ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT_Val,
927#endif
928 ADC_RES_16BIT_2SAMPL = ( 0x1 << 2) | 0x1,
929 ADC_RES_16BIT_4SAMPL = ( 0x2 << 2) | 0x1,
930 ADC_RES_16BIT_8SAMPL = ( 0x3 << 2) | 0x1,
931 ADC_RES_16BIT_16SAMPL = ( 0x4 << 2) | 0x1,
932 ADC_RES_16BIT_32SAMPL = ( 0x5 << 2) | 0x1,
933 ADC_RES_16BIT_64SAMPL = ( 0x6 << 2) | 0x1,
934 ADC_RES_16BIT_128SAMPL = ( 0x7 << 2) | 0x1,
935 ADC_RES_16BIT_256SAMPL = ( 0x8 << 2) | 0x1,
936 ADC_RES_16BIT_512SAMPL = ( 0x9 << 2) | 0x1,
937 ADC_RES_16BIT_1024SAMPL = ( 0xA << 2) | 0x1,
938 ADC_RES_14BIT = 0xfe,
939} adc_res_t;
940
941#define ADC_RES_16BIT ADC_RES_16BIT_16SAMPL
942#endif /* DOXYGEN */
943
948#ifndef ETH_RX_BUFFER_COUNT
949#define ETH_RX_BUFFER_COUNT (4)
950#endif
951
952#ifndef ETH_TX_BUFFER_COUNT
953#define ETH_TX_BUFFER_COUNT (4)
954#endif
955
956#ifndef ETH_RX_BUFFER_SIZE
957#define ETH_RX_BUFFER_SIZE (1536)
958#endif
959
960#ifndef ETH_TX_BUFFER_SIZE
961#define ETH_TX_BUFFER_SIZE (1536)
962#endif
968#if defined(GMAC_INST_NUM) || defined(DOXYGEN)
969typedef struct {
970 Gmac *dev;
971 gpio_t refclk;
972 gpio_t txen;
973 gpio_t txd0;
974 gpio_t txd1;
975 gpio_t crsdv;
976 gpio_t rxd0;
977 gpio_t rxd1;
978 gpio_t rxer;
979 gpio_t mdc;
980 gpio_t mdio;
981 gpio_t rst_pin;
982 gpio_t int_pin;
984#endif
985
989#define USBDEV_CPU_DMA_ALIGNMENT (4)
990
994#define USBDEV_CPU_DMA_REQUIREMENTS __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
995
999#if defined(USB_INST_NUM) || defined(DOXYGEN)
1000typedef struct {
1001 gpio_t dm;
1002 gpio_t dp;
1004 UsbDevice *device;
1005 uint8_t gclk_src;
1007#endif /* USB_INST_NUM */
1008
1012#define SDMMC_CPU_DMA_ALIGNMENT 4
1013
1017#define SDMMC_CPU_DMA_REQUIREMENTS __attribute__((aligned(SDMMC_CPU_DMA_ALIGNMENT)))
1018
1022typedef struct {
1023 void *sdhc;
1024 gpio_t cd;
1025 gpio_t wp;
1026} sdhc_conf_t;
1027
1032/* Limits are in clock cycles according to data sheet.
1033 As the WDT is clocked by a 1024 Hz clock, 1 cycle ≈ 1 ms */
1034#define NWDT_TIME_LOWER_LIMIT (8U)
1035#define NWDT_TIME_UPPER_LIMIT (16384U)
1041#define WDT_HAS_STOP (1)
1045#define WDT_HAS_INIT (1)
1046
1050typedef struct {
1051 gpio_t pin;
1052 uint8_t gclk_src;
1054
1055#if defined(REV_DMAC) || DOXYGEN
1105#define DMA_TRIGGER_DISABLED 0
1106
1110#if defined(CPU_COMMON_SAML21) || defined(DOXYGEN)
1111#define DMA_DESCRIPTOR_IN_LPSRAM
1112#endif
1113
1117#ifdef DMA_DESCRIPTOR_IN_LPSRAM
1118#define DMA_DESCRIPTOR_ATTRS __attribute__((section(".backup.bss")))
1119#else
1120#define DMA_DESCRIPTOR_ATTRS
1121#endif
1122
1126typedef unsigned dma_t;
1127
1137
1141void dma_init(void);
1142
1154
1161
1170void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq);
1171
1185void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst,
1186 size_t num, dma_incr_t incr);
1187
1208void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr);
1209
1230void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr);
1231
1251void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width,
1252 const void *src, void *dst, size_t num, dma_incr_t incr);
1253
1272void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src,
1273 size_t num, bool incr);
1274
1293void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num,
1294 bool incr);
1295
1302
1312void dma_wait(dma_t dma);
1313
1324#endif /* REV_DMAC || DOXYGEN */
1325
1335
1344int rtc_tamper_register(gpio_t pin, gpio_flank_t flank);
1345
1350
1359
1370uint8_t rtc_tamper_pin_mask(gpio_t pin);
1388
1392#ifdef FLASH_USER_PAGE_SIZE
1393#define FLASH_USER_PAGE_AUX_SIZE (FLASH_USER_PAGE_SIZE - sizeof(nvm_user_page_t))
1394#else
1395#define FLASH_USER_PAGE_AUX_SIZE (AUX_PAGE_SIZE * AUX_NB_OF_PAGES - sizeof(nvm_user_page_t))
1396#endif
1397
1407
1423void sam0_flashpage_aux_write(uint32_t offset, const void *data, size_t len);
1424
1432#define sam0_flashpage_aux_get(offset) \
1433 (const void*)((uint8_t*)NVMCTRL_USER + sizeof(nvm_user_page_t) + (offset))
1434
1440#define sam0_flashpage_aux_cfg() \
1441 ((const nvm_user_page_t*)NVMCTRL_USER)
1442
1445#ifdef __cplusplus
1446}
1447#endif
1448
1449#endif /* PERIPH_CPU_COMMON_H */
#define assert(cond)
abort the program if assertion is false
Definition assert.h:137
gpio_flank_t
Definition periph_cpu.h:180
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
i2c_speed_t
Definition periph_cpu.h:276
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:280
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:277
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:282
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:279
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
enum IRQn IRQn_Type
Interrupt Number Definition.
static void cortexm_sleep(int deep)
Put the CPU into (deep) sleep mode, using the WFI instruction.
Definition cpu.h:157
adc_res_t
Possible ADC resolution settings.
Definition adc.h:93
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:97
gpio_irq_trig_t
Definition of possible IRQ triggers.
Definition gpio_ll_irq.h:62
@ GPIO_TRIGGER_EDGE_FALLING
edge triggered IRQ on falling flanks only
Definition gpio_ll_irq.h:63
@ GPIO_TRIGGER_LEVEL_HIGH
level triggered IRQ on high input
Definition gpio_ll_irq.h:68
@ GPIO_TRIGGER_EDGE_RISING
edge triggered IRQ on rising flanks only
Definition gpio_ll_irq.h:65
@ GPIO_TRIGGER_EDGE_BOTH
edge triggered IRQ on falling AND rising flanks
Definition gpio_ll_irq.h:66
@ GPIO_TRIGGER_LEVEL_LOW
level triggered IRQ on low input
Definition gpio_ll_irq.h:69
gpio_pull_t
Enumeration of pull resistor configurations.
Definition gpio_ll.h:225
gpio_pull_strength_t
Enumeration of pull resistor values.
Definition gpio_ll.h:243
gpio_state_t
Enumeration of GPIO states (direction)
Definition gpio_ll.h:133
gpio_slew_t
Enumeration of slew rate settings.
Definition gpio_ll.h:307
gpio_drive_strength_t
Enumeration of drive strength options.
Definition gpio_ll.h:274
typedef gpio_conf_t
GPIO pin configuration.
Definition gpio_ll.h:391
@ GPIO_FLOATING
No pull ups nor pull downs enabled.
Definition gpio_ll.h:226
@ GPIO_PULL_KEEP
Keep the signal at current logic level with pull up/down resistors.
Definition gpio_ll.h:229
@ GPIO_PULL_DOWN
Pull down resistor enabled.
Definition gpio_ll.h:228
@ GPIO_PULL_UP
Pull up resistor enabled.
Definition gpio_ll.h:227
@ GPIO_PULL_WEAKEST
Use the weakest (highest Ohm value) resistor.
Definition gpio_ll.h:244
@ GPIO_PULL_WEAK
Use a weak pull resistor.
Definition gpio_ll.h:245
@ GPIO_PULL_STRONG
Use a strong pull resistor.
Definition gpio_ll.h:246
@ GPIO_PULL_STRONGEST
Use the strongest pull resistor.
Definition gpio_ll.h:247
@ GPIO_OUTPUT_OPEN_SOURCE
Use pin as output in open emitter configuration.
Definition gpio_ll.h:170
@ GPIO_USED_BY_PERIPHERAL
The GPIO pin is used by a peripheral.
Definition gpio_ll.h:189
@ GPIO_OUTPUT_OPEN_DRAIN
Use pin as output in open collector configuration.
Definition gpio_ll.h:157
@ GPIO_OUTPUT_PUSH_PULL
Use pin as output in push-pull configuration.
Definition gpio_ll.h:144
@ GPIO_DISCONNECT
Disconnect pin from all peripherals.
Definition gpio_ll.h:217
@ GPIO_INPUT
Use pin as input.
Definition gpio_ll.h:176
@ GPIO_SLEW_SLOWEST
let the output voltage level rise/fall as slow as possible
Definition gpio_ll.h:308
@ GPIO_SLEW_FAST
let the output voltage level rise/fall fast
Definition gpio_ll.h:311
@ GPIO_SLEW_SLOW
let the output voltage level rise/fall slowly
Definition gpio_ll.h:310
@ GPIO_SLEW_FASTEST
let the output voltage level rise/fall as fast as possible
Definition gpio_ll.h:312
@ GPIO_DRIVE_STRONG
Use a strong drive strength.
Definition gpio_ll.h:277
@ GPIO_DRIVE_WEAK
Use a weak drive strength.
Definition gpio_ll.h:276
@ GPIO_DRIVE_STRONGEST
Use the strongest drive strength.
Definition gpio_ll.h:278
@ GPIO_DRIVE_WEAKEST
Use the weakest drive strength.
Definition gpio_ll.h:275
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
#define GPIO_MODE(oe, ic, pr, dr)
Generate GPIO mode bitfields.
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition periph_cpu.h:518
@ UART_DATA_BITS_6
6 data bits
Definition periph_cpu.h:520
@ UART_DATA_BITS_5
5 data bits
Definition periph_cpu.h:519
@ UART_DATA_BITS_7
7 data bits
Definition periph_cpu.h:521
@ UART_DATA_BITS_8
8 data bits
Definition periph_cpu.h:522
uint8_t rtc_get_tamper_event(void)
Get and clear the RTC tamper event that has woken the CPU from Deep Sleep.
uart_rxpad_t
Available values for SERCOM UART RX pad selection.
@ UART_PAD_RX_1
select pad 1
@ UART_PAD_RX_0
use pad 0 for RX line
@ UART_PAD_RX_3
select pad 3
@ UART_PAD_RX_2
select pad 2
void gpio_disable_mux(gpio_t pin)
Disable alternate function (PMUX setting) for a PORT pin.
@ PB
port B
@ PC
port C
@ PA
port A
@ PD
port D
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
void dma_init(void)
Initialize DMA.
@ TIMER_TYPE_TC
Timer is a TC timer
@ TIMER_TYPE_TCC
Timer is a TCC timer.
int rtc_tamper_register(gpio_t pin, gpio_flank_t flank)
Enable Tamper Detection IRQs.
static uint8_t sercom_id(const void *sercom)
Return the numeric id of a SERCOM device derived from its address.
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
void dma_cancel(dma_t dma)
Cancel an active DMA transfer.
i2c_flag_t
Available SERCOM I2C flag selections.
@ I2C_FLAG_NONE
No flags set.
@ I2C_FLAG_RUN_STANDBY
run SERCOM in standby mode
void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr)
Prepare a transfer without modifying the source address settings.
void cpu_pm_cb_leave(int deep)
Called after the power management left a power mode.
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
uint32_t sam0_gclk_freq(uint8_t id)
Returns the frequency of a GCLK provider.
dma_t dma_acquire_channel(void)
Acquire a DMA channel.
spi_misopad_t
Available values for SERCOM SPI MISO pad selection.
@ SPI_PAD_MISO_1
use pad 1 for MISO line
@ SPI_PAD_MISO_2
use pad 2 for MISO line
@ SPI_PAD_MISO_0
use pad 0 for MISO line
@ SPI_PAD_MISO_3
use pad 3 for MISO line
void dma_release_channel(dma_t dma)
Release a previously acquired DMA channel.
void gpio_pm_cb_leave(int deep)
Called after the power management left a power mode.
static void sercom_set_gen(void *sercom, uint8_t gclk)
Configure generator clock for given SERCOM device.
uint8_t rtc_tamper_pin_mask(gpio_t pin)
Get the tamper event mask for a certain pin.
uart_flag_t
Available SERCOM UART flag selections.
@ UART_FLAG_TX_ONDEMAND
Only enable TX pin on demand.
@ UART_FLAG_NONE
No flags set.
@ UART_FLAG_RUN_STANDBY
run SERCOM in standby mode
@ UART_FLAG_WAKEUP
wake from sleep on receive
void sam0_flashpage_aux_reset(const nvm_user_page_t *cfg)
Reset the configuration area, apply a new configuration.
static void sam0_cortexm_sleep(int deep)
Wrapper for cortexm_sleep calling power management callbacks.
static void sercom_clk_dis(void *sercom)
Disable peripheral clock for given SERCOM device.
static bool cpu_woke_from_backup(void)
Returns true if the CPU woke deep sleep (backup/standby)
void cpu_pm_cb_enter(int deep)
Called before the power management enters a power mode.
void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying source and block si...
void sam0_flashpage_aux_write(uint32_t offset, const void *data, size_t len)
Write data to the user configuration area.
uart_txpad_t
Available values for SERCOM UART TX pad selection.
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
@ UART_PAD_TX_0
select pad 0
@ UART_PAD_TX_2
select pad 2
dma_incr_t
Available DMA address increment modes.
@ DMA_INCR_NONE
Don't increment any addresses after a beat.
@ DMA_INCR_DEST
Increment destination address after a beat.
@ DMA_INCR_BOTH
Increment both addresses after a beat.
@ DMA_INCR_SRC
Increment the source address after a beat.
void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Append a second transfer descriptor after the default channel descriptor.
void rtc_tamper_enable(void)
Enable Tamper Detection IRQs.
void rtc_tamper_init(void)
Power on the RTC (if the RTC/RTT is not otherwise used)
unsigned dma_t
DMA channel type.
void sam0_gclk_enable(uint8_t id)
Enables an on-demand GCLK that has been configured in cpu.c.
void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying destination and blo...
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
@ GPIO_MUX_E
select peripheral function E
@ GPIO_MUX_J
select peripheral function J
@ GPIO_MUX_K
select peripheral function K
@ GPIO_MUX_M
select peripheral function M
@ GPIO_MUX_H
select peripheral function H
@ GPIO_MUX_I
select peripheral function I
@ GPIO_MUX_D
select peripheral function D
@ GPIO_MUX_G
select peripheral function G
@ GPIO_MUX_C
select peripheral function C
@ GPIO_MUX_N
select peripheral function N
@ GPIO_MUX_A
select peripheral function A
@ GPIO_MUX_L
select peripheral function L
@ GPIO_MUX_B
select peripheral function B
@ GPIO_MUX_DISABLED
Disable
@ GPIO_MUX_F
select peripheral function F
static void sam0_set_voltage_regulator(sam0_supc_t src)
Switch the internal voltage regulator used for generating the internal MCU voltages.
spi_mosipad_t
Available values for SERCOM SPI MOSI and SCK pad selection.
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
@ SPI_PAD_MOSI_0_SCK_3
use pad 0 for MOSI, pad 3 for SCK
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
static void sercom_clk_en(void *sercom)
Enable peripheral clock for given SERCOM device.
sam0_supc_t
Available voltage regulators on the supply controller.
void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr)
Prepare a transfer without modifying the destination address settings.
void dma_start(dma_t dma)
Start a DMA transfer.
void gpio_pm_cb_enter(int deep)
Called before the power management enters a power mode.
ADC Channel Configuration.
uint32_t inputctrl
ADC channel pin multiplexer value
uint32_t muxpos
ADC channel pin multiplexer value.
Frequency meter configuration.
uint8_t gclk_src
GCLK source select for reference.
gpio_t pin
GPIO at which the frequency is to be measured.
I2C configuration structure.
Definition periph_cpu.h:299
uint8_t gclk_src
GCLK source which supplys SERCOM.
gpio_mux_t mux
alternate function (mux)
uint8_t flags
allow SERCOM to run in standby mode
SercomI2cm * dev
pointer to the used I2C device
PWM channel configuration data structure.
gpio_t pin
GPIO pin.
uint8_t chan
TCC channel to use.
gpio_mux_t mux
pin function multiplex value
PWM device configuration.
tc_tcc_cfg_t tim
timer configuration
uint8_t chan_numof
number of channels
const pwm_conf_chan_t * chan
channel configuration
uint8_t gclk_src
GCLK source which clocks TIMER.
NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on.
Definition periph_cpu.h:177
Ethernet parameters struct.
Gmac * dev
ptr to the device registers
gpio_t mdc
MII interface, clock gpio.
gpio_t mdio
MII interface, data gpio.
gpio_t rst_pin
PHY reset gpio.
gpio_t int_pin
PHY interrupt gpio.
USB peripheral parameters.
gpio_mux_t d_mux
alternate function (mux) for data pins
uint8_t gclk_src
GCLK source which supplys 48 MHz
UsbDevice * device
ptr to the device registers
SDHC peripheral configuration.
gpio_t wp
Write Protect pin (must be GPIO_UNDEF if not connected)
void * sdhc
SDHC peripheral.
gpio_t cd
Card Detect pin (must be GPIO_UNDEF if not connected)
SPI device configuration.
Definition periph_cpu.h:337
gpio_mux_t miso_mux
alternate function for MISO pin (mux)
spi_misopad_t miso_pad
pad to use for MISO line
gpio_mux_t clk_mux
alternate function for CLK pin (mux)
spi_mosipad_t mosi_pad
pad to use for MOSI and CLK line
gpio_mux_t mosi_mux
alternate function for MOSI pin (mux)
uint8_t gclk_src
GCLK source which supplys SERCOM.
void * dev
pointer to the used SPI device
Timer device configuration.
uint16_t flags
flags for CTRA, e.g.
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
uint8_t gclk_src
GCLK source which supplys Timer.
IRQn_Type irq
IRQ# of Timer Interrupt.
uint16_t gclk_ctrl
GCLK_CLKCTRL_ID for the Timer.
Tc * dev
pointer to the used Timer device
Common configuration for timer devices.
uint16_t gclk_id
TCn_GCLK_ID.
uint8_t type
Timer type (TC/TCC)
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
UART device configuration.
Definition periph_cpu.h:218
gpio_mux_t mux
alternative function for pins
uint8_t gclk_src
GCLK source which supplys SERCOM.
uart_txpad_t tx_pad
pad selection for TX line
SercomUsart * dev
pointer to the used UART device
uart_rxpad_t rx_pad
pad selection for RX line
uart_flag_t flags
set optional SERCOM flags
GPIO pin configuration for SAM0 MCUs.
bool initial_value
Initial value of the output.
uint8_t bits
the raw bits
gpio_pull_t pull
Pull resistor configuration.
gpio_state_t state
State of the pin.
gpio_drive_strength_t drive_strength
Drive strength of the GPIO.