sam0_common/include/periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CPU_COMMON_H
21 #define PERIPH_CPU_COMMON_H
22 
23 #include "cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
32 #define CPUID_LEN (16U)
33 
38 #define PERIPH_SPI_NEEDS_INIT_CS
39 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
40 #define PERIPH_SPI_NEEDS_TRANSFER_REG
41 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
42 
48 #define HAVE_GPIO_T
49 typedef uint32_t gpio_t;
55 #define GPIO_UNDEF (0xffffffff)
56 
61 #define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
62 
67 #define PM_NUM_MODES (3)
68 
70 #ifndef DOXYGEN
71 
75 #define HAVE_GPIO_FLANK_T
76 typedef enum {
77  GPIO_FALLING = 2,
78  GPIO_RISING = 1,
79  GPIO_BOTH = 3
80 } gpio_flank_t;
82 #endif /* ndef DOXYGEN */
83 
87 typedef enum {
88  GPIO_MUX_A = 0x0,
89  GPIO_MUX_B = 0x1,
90  GPIO_MUX_C = 0x2,
91  GPIO_MUX_D = 0x3,
92  GPIO_MUX_E = 0x4,
93  GPIO_MUX_F = 0x5,
94  GPIO_MUX_G = 0x6,
95  GPIO_MUX_H = 0x7,
96 } gpio_mux_t;
97 
101 typedef enum {
106 } uart_rxpad_t;
107 
111 typedef enum {
116 } uart_txpad_t;
117 
121 typedef enum {
125 } uart_flag_t;
126 
130 typedef struct {
131  SercomUsart *dev;
132  gpio_t rx_pin;
133  gpio_t tx_pin;
138  uint32_t gclk_src;
139 } uart_conf_t;
140 
144 typedef enum {
149 } spi_misopad_t;
150 
154 typedef enum {
159 } spi_mosipad_t;
160 
165 #define HAVE_SPI_MODE_T
166 typedef enum {
167  SPI_MODE_0 = 0x0,
168  SPI_MODE_1 = 0x1,
169  SPI_MODE_2 = 0x2,
170  SPI_MODE_3 = 0x3
171 } spi_mode_t;
178 #define HAVE_SPI_CLK_T
179 typedef enum {
180  SPI_CLK_100KHZ = 100000U,
181  SPI_CLK_400KHZ = 400000U,
182  SPI_CLK_1MHZ = 1000000U,
183  SPI_CLK_5MHZ = 5000000U,
184  SPI_CLK_10MHZ = 10000000U
185 } spi_clk_t;
191 typedef struct {
192  SercomSpi *dev;
193  gpio_t miso_pin;
194  gpio_t mosi_pin;
195  gpio_t clk_pin;
201 } spi_conf_t;
202 
209 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
210 
218 static inline int sercom_id(void *sercom)
219 {
220 #if defined(CPU_FAM_SAMD21)
221  return ((((uint32_t)sercom) >> 10) & 0x7) - 2;
222 #elif defined(CPU_FAM_SAML21)
223  return ((((uint32_t)sercom) >> 10) & 0x7);
224 #endif
225 }
226 
232 static inline void sercom_clk_en(void *sercom)
233 {
234 #if defined(CPU_FAM_SAMD21)
235  PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(sercom));
236 #elif defined(CPU_FAM_SAML21)
237  if (sercom_id(sercom) < 5) {
238  MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
239  } else {
240  MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
241  }
242 #endif
243 }
244 
250 static inline void sercom_clk_dis(void *sercom)
251 {
252 #if defined(CPU_FAM_SAMD21)
253  PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(sercom));
254 #elif defined(CPU_FAM_SAML21)
255  if (sercom_id(sercom) < 5) {
256  MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
257  } else {
258  MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
259  }
260 #endif
261 }
262 
269 static inline void sercom_set_gen(void *sercom, uint32_t gclk)
270 {
271 #if defined(CPU_FAM_SAMD21)
272  GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | gclk |
273  (SERCOM0_GCLK_ID_CORE + sercom_id(sercom)));
274  while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
275 #elif defined(CPU_FAM_SAML21)
276  GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + sercom_id(sercom)].reg =
277  (GCLK_PCHCTRL_CHEN | gclk);
278 #endif
279 }
280 
284 typedef struct {
285  gpio_t pin;
286  uint32_t muxpos;
288 
289 
290 #ifdef __cplusplus
291 }
292 #endif
293 
294 #endif /* PERIPH_CPU_COMMON_H */
295 
select peripheral function D
static int sercom_id(void *sercom)
Return the numeric id of a SERCOM device derived from its address.
emit interrupt on rising flank
uart_flag_t
Available SERCOM UART flag selections.
uint32_t gclk_src
GCLK source which supplys SERCOM.
select peripheral function E
gpio_mux_t clk_mux
alternate function for CLK pin (mux)
select peripheral function B
spi_misopad_t
Available values for SERCOM SPI MISO pad selection.
SercomSpi * dev
pointer to the used SPI device
uart_txpad_t
Available values for SERCOM UART TX pad selection.
select peripheral function F
drive the SPI bus with 100KHz
spi_mosipad_t mosi_pad
pad to use for MOSI and CLK line
drive the SPI bus with 400KHz
ADC Channel Configuration.
SercomUsart * dev
pointer to the used UART device
emit interrupt on both flanks
select peripheral function H
uart_txpad_t tx_pad
pad selection for TX line
select peripheral function C
gpio_mux_t mosi_mux
alternate function for MOSI pin (mux)
uint32_t muxpos
ADC channel pin multiplexer value.
spi_misopad_t miso_pad
pad to use for MISO line
select peripheral function G
select peripheral function A
uart_rxpad_t
Available values for SERCOM UART RX pad selection.
gpio_mux_t miso_mux
alternate function for MISO pin (mux)
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
drive the SPI bus with 5MHz
static void sercom_set_gen(void *sercom, uint32_t gclk)
Configure generator clock for given SERCOM device.
static void sercom_clk_en(void *sercom)
Enable peripheral clock for given SERCOM device.
uart_rxpad_t rx_pad
pad selection for RX line
drive the SPI bus with 10MHz
emit interrupt on falling flank
drive the SPI bus with 1MHz
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
use pad 3 for MOSI, pad 1 for SCK
use pad 0 for MOSI, pad 3 for SCK
UART device configuration.
spi_mosipad_t
Available values for SERCOM SPI MOSI and SCK pad selection.
use pad 2 for MOSI, pad 3 for SCK
uart_flag_t flags
set optional SERCOM flags
SPI module configuration options.
gpio_mux_t mux
alternative function for pins
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
use pad 0 for MOSI, pad 1 for SCK
static void sercom_clk_dis(void *sercom)
Disable peripheral clock for given SERCOM device.