periph_conf_common.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
20 #ifndef PERIPH_CONF_COMMON_H
21 #define PERIPH_CONF_COMMON_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* high speed clock configuration:
34  * 0 := use internal HSI oscillator (always 8MHz)
35  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
36  * must be 4000000 <= value <= 16000000 */
37 #define CLOCK_HSE (16000000U)
38 /* low speed clock configuration:
39  * 0 := use internal LSI oscillator (~40kHz)
40  * 1 := use extern LSE oscillator, always 32.768kHz */
41 #define CLOCK_LSE (1)
42 /* targeted system clock speed [in Hz], must be <= 72MHz */
43 #define CLOCK_CORECLOCK (72000000U)
44 /* PLL configuration, set both values to zero to disable PLL usage. The values
45  * must be set to satisfy the following equation:
46  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
47  * with
48  * 1 <= CLOCK_PLL_DIV <= 2
49  * 2 <= CLOCK_PLL_MUL <= 17 */
50 #define CLOCK_PLL_DIV (2)
51 #define CLOCK_PLL_MUL (9)
52 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
53  * ABP1 <= 36MHz
54  */
55 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
56 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
57 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
58 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
59 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
60 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
61 
67 #define ADC_CONFIG { \
68  { GPIO_PIN(PORT_A,3), 0, 3 }, \
69  { GPIO_UNDEF , 0, 16 }, \
70  { GPIO_UNDEF , 0, 17 } }
71 
72 #define ADC_NUMOF (3)
73 
79 static const timer_conf_t timer_config[] = {
80  {
81  .dev = TIM2,
82  .max = 0x0000ffff,
83  .rcc_mask = RCC_APB1ENR_TIM2EN,
84  .bus = APB1,
85  .irqn = TIM2_IRQn
86  },
87  {
88  .dev = TIM3,
89  .max = 0x0000ffff,
90  .rcc_mask = RCC_APB1ENR_TIM3EN,
91  .bus = APB1,
92  .irqn = TIM3_IRQn
93  }
94 };
95 
96 #define TIMER_0_ISR isr_tim2
97 #define TIMER_1_ISR isr_tim3
98 
99 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
100 
106 static const uart_conf_t uart_config[] = {
107  {
108  .dev = USART1,
109  .rcc_mask = RCC_APB2ENR_USART1EN,
110  .rx_pin = GPIO_PIN(PORT_A, 10),
111  .tx_pin = GPIO_PIN(PORT_A, 9),
112  .bus = APB2,
113  .irqn = USART1_IRQn
114  },
115  {
116  .dev = USART2,
117  .rcc_mask = RCC_APB1ENR_USART2EN,
118  .rx_pin = GPIO_PIN(PORT_A, 3),
119  .tx_pin = GPIO_PIN(PORT_A, 2),
120  .bus = APB1,
121  .irqn = USART2_IRQn
122  }
123 };
124 
125 #define UART_0_ISR (isr_usart1)
126 #define UART_1_ISR (isr_usart2)
127 
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
135 #define RTT_NUMOF (1U)
136 #define RTT_IRQ_PRIO 1
137 
138 #define RTT_DEV RTC
139 #define RTT_IRQ RTC_IRQn
140 #define RTT_ISR isr_rtc
141 #define RTT_MAX_VALUE (0xffffffff)
142 #define RTT_FREQUENCY (1) /* in Hz */
143 #define RTT_PRESCALER (0x7fff) /* run with 1 Hz */
144 
150 #define I2C_NUMOF (1U)
151 #define I2C_0_EN 1
152 #define I2C_IRQ_PRIO 1
153 #define I2C_APBCLK (CLOCK_APB1)
154 
155 /* I2C 0 device configuration */
156 #define I2C_0_DEV I2C1
157 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
158 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
159 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
160 #define I2C_0_EVT_ISR isr_i2c1_ev
161 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
162 #define I2C_0_ERR_ISR isr_i2c1_er
163 /* I2C 0 pin configuration */
164 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B,6)
165 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
166 
174 static const uint8_t spi_divtable[2][5] = {
175  { /* for APB1 @ 36000000Hz */
176  7, /* -> 140625Hz */
177  6, /* -> 281250Hz */
178  4, /* -> 1125000Hz */
179  2, /* -> 4500000Hz */
180  1 /* -> 9000000Hz */
181  },
182  { /* for APB2 @ 72000000Hz */
183  7, /* -> 281250Hz */
184  7, /* -> 281250Hz */
185  5, /* -> 1125000Hz */
186  3, /* -> 4500000Hz */
187  2 /* -> 9000000Hz */
188  }
189 };
190 
191 #ifdef __cplusplus
192 }
193 #endif
194 
195 #endif /* PERIPH_CONF_COMMON_H */
196 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
UART device configuration.
cc2538_gptimer_t * dev
timer device
Timer configuration data.