20 #ifndef PERIPH_CONF_COMMON_H 21 #define PERIPH_CONF_COMMON_H 23 #include "periph_cpu.h" 39 #define CLOCK_CORECLOCK (72000000U) 42 #define CLOCK_HSE (16000000U) 47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1) 49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2) 51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1) 55 #define CLOCK_PLL_PREDIV (2) 56 #define CLOCK_PLL_MUL (9) 63 #define ADC_CONFIG { \ 64 { GPIO_PIN(PORT_A,3), 0, 3 }, \ 65 { GPIO_UNDEF , 0, 16 }, \ 66 { GPIO_UNDEF , 0, 17 } } 79 .rcc_mask = RCC_APB1ENR_TIM2EN,
86 .rcc_mask = RCC_APB1ENR_TIM3EN,
92 #define TIMER_0_ISR isr_tim2 93 #define TIMER_1_ISR isr_tim3 95 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) 105 .rcc_mask = RCC_APB2ENR_USART1EN,
113 .rcc_mask = RCC_APB1ENR_USART2EN,
121 #define UART_0_ISR (isr_usart1) 122 #define UART_1_ISR (isr_usart2) 124 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) 131 #define RTT_NUMOF (1U) 132 #define RTT_IRQ_PRIO 1 135 #define RTT_IRQ RTC_IRQn 136 #define RTT_ISR isr_rtc 137 #define RTT_MAX_VALUE (0xffffffff) 138 #define RTT_FREQUENCY (1) 139 #define RTT_PRESCALER (0x7fff) 146 #define I2C_NUMOF (1U) 148 #define I2C_IRQ_PRIO 1 149 #define I2C_APBCLK (CLOCK_APB1) 152 #define I2C_0_DEV I2C1 153 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN)) 154 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN)) 155 #define I2C_0_EVT_IRQ I2C1_EV_IRQn 156 #define I2C_0_EVT_ISR isr_i2c1_ev 157 #define I2C_0_ERR_IRQ I2C1_ER_IRQn 158 #define I2C_0_ERR_ISR isr_i2c1_er 160 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B,6) 161 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7) cc2538_uart_t * dev
pointer to the used UART device
NRF_TIMER_Type * dev
timer device
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
UART device configuration.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.