periph_conf_common.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
20 #ifndef PERIPH_CONF_COMMON_H
21 #define PERIPH_CONF_COMMON_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 72MHz */
39  #define CLOCK_CORECLOCK (72000000U)
40  /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42  #define CLOCK_HSE (16000000U)
43  /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45  #define CLOCK_LSE (1)
46  /* peripheral clock setup */
47  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49  #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
50  #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51  #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
52  #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54  /* PLL factors */
55  #define CLOCK_PLL_PREDIV (2)
56  #define CLOCK_PLL_MUL (9)
57 
63 #define ADC_CONFIG { \
64  { GPIO_PIN(PORT_A,3), 0, 3 }, \
65  { GPIO_UNDEF , 0, 16 }, \
66  { GPIO_UNDEF , 0, 17 } }
67 
68 #define ADC_NUMOF (3)
69 
75 static const timer_conf_t timer_config[] = {
76  {
77  .dev = TIM2,
78  .max = 0x0000ffff,
79  .rcc_mask = RCC_APB1ENR_TIM2EN,
80  .bus = APB1,
81  .irqn = TIM2_IRQn
82  },
83  {
84  .dev = TIM3,
85  .max = 0x0000ffff,
86  .rcc_mask = RCC_APB1ENR_TIM3EN,
87  .bus = APB1,
88  .irqn = TIM3_IRQn
89  }
90 };
91 
92 #define TIMER_0_ISR isr_tim2
93 #define TIMER_1_ISR isr_tim3
94 
95 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
96 
102 static const uart_conf_t uart_config[] = {
103  {
104  .dev = USART1,
105  .rcc_mask = RCC_APB2ENR_USART1EN,
106  .rx_pin = GPIO_PIN(PORT_A, 10),
107  .tx_pin = GPIO_PIN(PORT_A, 9),
108  .bus = APB2,
109  .irqn = USART1_IRQn
110  },
111  {
112  .dev = USART2,
113  .rcc_mask = RCC_APB1ENR_USART2EN,
114  .rx_pin = GPIO_PIN(PORT_A, 3),
115  .tx_pin = GPIO_PIN(PORT_A, 2),
116  .bus = APB1,
117  .irqn = USART2_IRQn
118  }
119 };
120 
121 #define UART_0_ISR (isr_usart1)
122 #define UART_1_ISR (isr_usart2)
123 
124 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
125 
131 #define RTT_NUMOF (1U)
132 #define RTT_IRQ_PRIO 1
133 
134 #define RTT_DEV RTC
135 #define RTT_IRQ RTC_IRQn
136 #define RTT_ISR isr_rtc
137 #define RTT_MAX_VALUE (0xffffffff)
138 #define RTT_FREQUENCY (1) /* in Hz */
139 #define RTT_PRESCALER (0x7fff) /* run with 1 Hz */
140 
146 #define I2C_NUMOF (1U)
147 #define I2C_0_EN 1
148 #define I2C_IRQ_PRIO 1
149 #define I2C_APBCLK (CLOCK_APB1)
150 
151 /* I2C 0 device configuration */
152 #define I2C_0_DEV I2C1
153 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
154 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
155 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
156 #define I2C_0_EVT_ISR isr_i2c1_ev
157 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
158 #define I2C_0_ERR_ISR isr_i2c1_er
159 /* I2C 0 pin configuration */
160 #define I2C_0_SCL_PIN GPIO_PIN(PORT_B,6)
161 #define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
162 
170 static const uint8_t spi_divtable[2][5] = {
171  { /* for APB1 @ 36000000Hz */
172  7, /* -> 140625Hz */
173  6, /* -> 281250Hz */
174  4, /* -> 1125000Hz */
175  2, /* -> 4500000Hz */
176  1 /* -> 9000000Hz */
177  },
178  { /* for APB2 @ 72000000Hz */
179  7, /* -> 281250Hz */
180  7, /* -> 281250Hz */
181  5, /* -> 1125000Hz */
182  3, /* -> 4500000Hz */
183  2 /* -> 9000000Hz */
184  }
185 };
186 
187 #ifdef __cplusplus
188 }
189 #endif
190 
191 #endif /* PERIPH_CONF_COMMON_H */
192 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
UART device configuration.
Timer configuration.