mtd_spi_nor.h
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1 /*
2  * Copyright (C) 2016 Eistec AB
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
24 #ifndef MTD_SPI_NOR_H_
25 #define MTD_SPI_NOR_H_
26 
27 #include <stdint.h>
28 
29 #include "periph_conf.h"
30 #include "periph/spi.h"
31 #include "periph/gpio.h"
32 #include "mtd.h"
33 
34 #ifdef __cplusplus
35 extern "C"
36 {
37 #endif
38 
42 typedef struct {
43  uint8_t rdid;
44  uint8_t wren;
45  uint8_t rdsr;
46  uint8_t wrsr;
47  uint8_t read;
48  uint8_t read_fast;
49  uint8_t page_program;
50  uint8_t sector_erase;
51  uint8_t block_erase_32k;
52  uint8_t block_erase;
53  uint8_t chip_erase;
54  uint8_t sleep;
55  uint8_t wake;
56  /* TODO: enter 4 byte address mode for large memories */
58 
64 typedef struct __attribute__((packed)) {
65  uint8_t bank;
66  uint8_t manuf;
67  uint8_t device[2];
69 
75 #define JEDEC_NEXT_BANK (0x7f)
76 
80 #define SPI_NOR_F_SECT_4K (1)
81 
84 #define SPI_NOR_F_SECT_32K (2)
85 
91 typedef struct {
95  gpio_t cs;
98  uint16_t flag;
105  uint32_t page_addr_mask;
111  uint32_t sec_addr_mask;
112  uint8_t addr_width;
124  uint8_t sec_addr_shift;
125 } mtd_spi_nor_t;
126 
130 extern const mtd_desc_t mtd_spi_nor_driver;
131 
132 /* Available opcode tables for known devices */
133 /* Defined in mtd_spi_nor_configs.c */
142 
143 #ifdef __cplusplus
144 }
145 #endif
146 
147 #endif /* MTD_SPI_NOR_H_ */
148 
uint8_t chip_erase
Chip erase.
Definition: mtd_spi_nor.h:53
uint8_t bank
Manufacturer ID bank number, 1 through 10, see JEP106.
Definition: mtd_spi_nor.h:65
uint8_t wren
Write enable.
Definition: mtd_spi_nor.h:44
const mtd_desc_t mtd_spi_nor_driver
NOR flash SPI MTD device operations table.
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default
Default command opcodes.
uint8_t sector_erase
Block erase 4 KiB.
Definition: mtd_spi_nor.h:50
const mtd_spi_nor_opcode_t * opcode
Opcode table for the device.
Definition: mtd_spi_nor.h:93
uint8_t wake
Release from deep power down.
Definition: mtd_spi_nor.h:55
MTD driver interface.
Definition: mtd.h:75
Device descriptor for serial flash memory devices.
Definition: mtd_spi_nor.h:91
Low-level GPIO peripheral driver interface definitions.
uint8_t page_addr_shift
number of right shifts to get the address to the start of the page
Definition: mtd_spi_nor.h:118
spi_mode_t mode
SPI mode.
Definition: mtd_spi_nor.h:96
uint8_t read
Read data bytes, 3 byte address.
Definition: mtd_spi_nor.h:47
uint8_t sec_addr_shift
number of right shifts to get the address to the start of the sector
Definition: mtd_spi_nor.h:124
mtd_jedec_id_t jedec_id
JEDEC ID of the chip.
Definition: mtd_spi_nor.h:99
uint8_t block_erase
Block erase (usually 64 KiB)
Definition: mtd_spi_nor.h:52
uint8_t rdid
Read identification (JEDEC ID)
Definition: mtd_spi_nor.h:43
uint8_t manuf
Manufacturer ID, 1 byte.
Definition: mtd_spi_nor.h:66
mtd_dev_t base
inherit from mtd_dev_t object
Definition: mtd_spi_nor.h:92
Low-level SPI peripheral driver interface definition.
uint8_t block_erase_32k
32KiB block erase
Definition: mtd_spi_nor.h:51
uint16_t flag
Config flags.
Definition: mtd_spi_nor.h:98
spi_t spi
SPI bus the device is connected to.
Definition: mtd_spi_nor.h:94
uint8_t rdsr
Read status register.
Definition: mtd_spi_nor.h:45
gpio_t cs
CS pin GPIO handle.
Definition: mtd_spi_nor.h:95
uint8_t sleep
Deep power down.
Definition: mtd_spi_nor.h:54
MTD device descriptor.
Definition: mtd.h:58
uint32_t sec_addr_mask
bitmask to corresponding to the sector address
Definition: mtd_spi_nor.h:111
uint8_t wrsr
Write status register.
Definition: mtd_spi_nor.h:46
Internal representation of JEDEC memory ID codes.
Definition: mtd_spi_nor.h:64
uint32_t page_addr_mask
bitmask to corresponding to the page address
Definition: mtd_spi_nor.h:105
uint8_t read_fast
Read data bytes, 3 byte address, at higher speed.
Definition: mtd_spi_nor.h:48
SPI NOR flash opcode table.
Definition: mtd_spi_nor.h:42
uint8_t page_program
Page program.
Definition: mtd_spi_nor.h:49
spi_clk_t clk
SPI clock.
Definition: mtd_spi_nor.h:97
uint8_t addr_width
Number of bytes in addresses, usually 3 for small devices.
Definition: mtd_spi_nor.h:112
unsigned int spi_t
Default type for SPI devices.
Definition: spi.h:105