periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdbool.h>
25 #include "cpu.h"
26 #include "msp430_regs.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define HAVE_GPIO_T
37 typedef uint16_t gpio_t;
43 #define GPIO_UNDEF (0xffff)
44 
49 #define GPIO_PIN(x, y) ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0x07))))
50 
54 #define SPI_HWCS(x) (SPI_CS_UNDEF)
55 
56 #ifndef DOXYGEN
57 
61 #define HAVE_GPIO_FLANK_T
62 typedef enum {
63  GPIO_FALLING = 0xff,
64  GPIO_RISING = 0x00,
65  GPIO_BOTH = 0xab
66 } gpio_flank_t;
72 #define HAVE_SPI_MODE_T
73 #ifndef SPI_USE_USCI
74 typedef enum {
75  SPI_MODE_0 = (USART_TCTL_CKPH),
76  SPI_MODE_1 = 0,
77  SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH),
78  SPI_MODE_3 = (USART_TCTL_CKPL)
79 } spi_mode_t;
80 #else
81 typedef enum {
82  SPI_MODE_0 = (USCI_SPI_CTL0_CKPH),
83  SPI_MODE_1 = 0,
84  SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH),
85  SPI_MODE_3 = (USCI_SPI_CTL0_CKPL)
86 } spi_mode_t;
87 #endif
88 
93 #define HAVE_SPI_CLK_T
94 typedef enum {
95  SPI_CLK_100KHZ = 100000,
96  SPI_CLK_400KHZ = 400000,
97  SPI_CLK_1MHZ = 1000000,
98  SPI_CLK_5MHZ = 5000000,
99  SPI_CLK_10MHZ = 0,
100 } spi_clk_t;
102 #endif /* ndef DOXYGEN */
103 
107 enum {
108  P1 = 1,
109  P2 = 2,
110  P3 = 3,
111  P4 = 4,
112  P5 = 5,
113  P6 = 6,
114 };
115 
122 void gpio_periph_mode(gpio_t pin, bool enable);
123 
128 #define PERIPH_SPI_NEEDS_INIT_CS
129 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
130 #define PERIPH_SPI_NEEDS_TRANSFER_REG
131 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
132 
134 #ifdef __cplusplus
135 }
136 #endif
137 
138 #endif /* PERIPH_CPU_H */
139 
CPOL=0, CPHA=1.
Definition: periph_cpu.h:218
emit interrupt on rising flank
Definition: periph_cpu.h:93
gpio_flank_t
Definition: periph_cpu.h:91
PORT 6.
Definition: periph_cpu.h:113
spi_mode_t
CPOL=0, CPHA=0.
Definition: periph_cpu.h:217
drive the SPI bus with 100KHz
Definition: periph_cpu.h:230
drive the SPI bus with 400KHz
Definition: periph_cpu.h:231
PORT 3.
Definition: periph_cpu.h:110
PORT 2.
Definition: periph_cpu.h:109
emit interrupt on both flanks
Definition: periph_cpu.h:95
void gpio_periph_mode(gpio_t pin, bool enable)
Enable or disable a pin to be used by peripheral modules.
CPOL=1, CPHA=1.
Definition: periph_cpu.h:220
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
Cortex CMSIS style definition of MSP430 registers.
drive the SPI bus with 5MHz
Definition: periph_cpu.h:233
drive the SPI bus with 10MHz
Definition: periph_cpu.h:234
emit interrupt on falling flank
Definition: periph_cpu.h:94
drive the SPI bus with 1MHz
Definition: periph_cpu.h:232
PORT 5.
Definition: periph_cpu.h:112
PORT 1.
Definition: periph_cpu.h:108
PORT 4.
Definition: periph_cpu.h:111
CPOL=1, CPHA=0.
Definition: periph_cpu.h:219
spi_clk_t
Definition: periph_cpu.h:229