msp430_regs.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
23 #ifndef MSP430_REGS_H
24 #define MSP430_REGS_H
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #define REG8 volatile uint8_t
34 
38 #define REG16 volatile uint16_t
39 
43 typedef struct {
50 } msp_sfr_t;
51 
55 typedef struct {
56  REG8 IN;
57  REG8 OD;
60 } msp_port_t;
61 
65 typedef struct {
66  REG8 IN;
67  REG8 OD;
71  REG8 IE;
74 
78 typedef struct {
87 } msp_usart_t;
88 
92 typedef struct {
112 } msp_usci_t;
113 
117 typedef struct {
127 
131 typedef struct {
133  REG16 reserved[7];
136 
140 typedef struct {
141  REG16 CTL;
142  REG16 CCTL[7];
143  REG16 R;
144  REG16 CCR[7];
145 } msp_timer_t;
146 
151 #define SFR_IE1_OFIE (0x02)
152 #define SFR_IE1_URXIE0 (0x40)
153 #define SFR_IE1_UTXIE0 (0x80)
154 
160 #define SFR_IE2_UCA0RXIE (0x01)
161 #define SFR_IE2_UCA0TXIE (0x02)
162 #define SFR_IE2_URXIE2 (0x10)
163 #define SFR_IE2_UTXIE2 (0x20)
164 
170 #define SFR_IFG1_OFIFG (0x02)
171 #define SFR_IFG1_URXIFG0 (0x40)
172 #define SFR_IFG1_UTXIFG0 (0x80)
173 
179 #define SFR_IFG2_UCA0RXIFG (0x01)
180 #define SFR_IFG2_UCA0TXIFG (0x02)
181 #define SFR_IFG2_URXIFG1 (0x10)
182 #define SFR_IFG2_UTXIFG1 (0x20)
183 
189 #define SFR_ME1_USPIE0 (0x40)
190 
196 #define SFR_ME2_USPIE1 (0x10)
197 
203 #define USART_CTL_SWRST (0x01)
204 #define USART_CTL_MM (0x02)
205 #define USART_CTL_SYNC (0x04)
206 #define USART_CTL_LISTEN (0x08)
207 #define USART_CTL_CHAR (0x10)
208 #define USART_CTL_SPB (0x20)
209 #define USART_CTL_PEV (0x40)
210 #define USART_CTL_PENA (0x80)
211 
217 #define USART_TCTL_TXEPT (0x01)
218 #define USART_TCTL_STC (0x02)
219 #define USART_TCTL_TXWAKE (0x04)
220 #define USART_TCTL_URXSE (0x08)
221 #define USART_TCTL_SSEL_MASK (0x30)
222 #define USART_TCTL_SSEL_UCLKI (0x00)
223 #define USART_TCTL_SSEL_ACLK (0x10)
224 #define USART_TCTL_SSEL_SMCLK (0x20)
225 #define USART_TCTL_CKPL (0x40)
226 #define USART_TCTL_CKPH (0x80)
227 
233 #define USART_RCTL_RXERR (0x01)
234 #define USART_RCTL_RXWAKE (0x02)
235 #define USART_RCTL_URXWIE (0x04)
236 #define USART_RCTL_URXEIE (0x08)
237 #define USART_RCTL_BRK (0x10)
238 #define USART_RCTL_OE (0x20)
239 #define USART_RCTL_PE (0x40)
240 #define USART_RCTL_FE (0x80)
241 
247 #define USCI_ACTL0_UCSYNC (0x01)
248 #define USCI_ACTL0_MODE_MASK (0x06)
249 #define USCI_ACTL0_MODE_UART (0x00)
250 #define USCI_ACTL0_MODE_ILMM (0x02)
251 #define USCI_ACTL0_MODE_ABMM (0x04)
252 #define USCI_ACTL0_MODE_UART_ABR (0x06)
253 #define USCI_ACTL0_SPB (0x08)
254 #define USCI_ACTL0_7BIT (0x10)
255 #define USCI_ACTL0_MSB (0x20)
256 #define USCI_ACTL0_PAR (0x40)
257 #define USCI_ACTL0_PEN (0x80)
258 
264 #define USCI_SPI_CTL0_UCSYNC (0x01)
265 #define USCI_SPI_CTL0_MODE_3 (0x06)
266 #define USCI_SPI_CTL0_MODE_0 (0x00)
267 #define USCI_SPI_CTL0_MODE_1 (0x02)
268 #define USCI_SPI_CTL0_MODE_2 (0x04)
269 #define USCI_SPI_CTL0_MST (0x08)
270 #define USCI_SPI_CTL0_7BIT (0x10)
271 #define USCI_SPI_CTL0_MSB (0x20)
272 #define USCI_SPI_CTL0_CKPL (0x40)
273 #define USCI_SPI_CTL0_CKPH (0x80)
274 
280 #define USCI_SPI_STAT_UCBUSY (0x01)
281 #define USCI_SPI_STAT_UCOE (0x20)
282 #define USCI_SPI_STAT_UCFE (0x40)
283 #define USCI_SPI_STAT_UCLISTEN (0x80)
284 
290 #define USCI_ACTL1_SWRST (0x01)
291 #define USCI_ACTL1_TXBRK (0x02)
292 #define USCI_ACTL1_TXADDR (0x04)
293 #define USCI_ACTL1_DORM (0x08)
294 #define USCI_ACTL1_BRKIE (0x10)
295 #define USCI_ACTL1_RXEIE (0x20)
296 #define USCI_ACTL1_SSEL_MASK (0xc0)
297 #define USCI_ACTL1_SSEL_UCLK (0x00)
298 #define USCI_ACTL1_SSEL_ACLK (0x40)
299 #define USCI_ACTL1_SSEL_SMCLK (0xc0)
300 
306 #define USCI_SPI_CTL1_SWRST (0x01)
307 #define USCI_SPI_CTL1_SSEL_MASK (0xc0)
308 #define USCI_SPI_CTL1_SSEL_NA (0x00)
309 #define USCI_SPI_CTL1_SSEL_ACLK (0x40)
310 #define USCI_SPI_CTL1_SSEL_SMCLK (0xc0)
311 
317 #define USCI_AMCTL_OS16 (0x01)
318 #define USCI_AMCTL_BRS_MASK (0xe0)
319 #define USCI_AMCTL_BRS_SHIFT (1U)
320 #define USCI_AMCTL_BRF_MASK (0xf0)
321 #define USCI_AMCTL_BRF_SHIFT (4U)
322 
328 #define USCI_ASTAT_BUSY (0x01)
329 #define USCI_ASTAT_IDLE (0x02)
330 #define USCI_ASTAT_ADDR (0x02)
331 #define USCI_ASTAT_RXERR (0x04)
332 #define USCI_ASTAT_BRK (0x08)
333 #define USCI_ASTAT_PE (0x10)
334 #define USCI_ASTAT_OE (0x20)
335 #define USCI_ASTAT_FE (0x40)
336 #define USCI_ASTAT_LISTEN (0x80)
337 
343 #define TIMER_CTL_IFG (0x0001)
344 #define TIMER_CTL_IE (0x0002)
345 #define TIMER_CTL_CLR (0x0004)
346 #define TIMER_CTL_MC_MASK (0x0030)
347 #define TIMER_CTL_MC_STOP (0x0000)
348 #define TIMER_CTL_MC_UP (0x0010)
349 #define TIMER_CTL_MC_CONT (0x0020)
350 #define TIMER_CTL_MC_UPDOWN (0x0030)
351 #define TIMER_CTL_ID_MASK (0x00c0)
352 #define TIMER_CTL_ID_DIV1 (0x0000)
353 #define TIMER_CTL_ID_DIV2 (0x0040)
354 #define TIMER_CTL_ID_DIV4 (0x0080)
355 #define TIMER_CTL_ID_DIV8 (0x00c0)
356 #define TIMER_CTL_TASSEL_MASK (0x0300)
357 #define TIMER_CTL_TASSEL_TCLK (0x0000)
358 #define TIMER_CTL_TASSEL_ACLK (0x0100)
359 #define TIMER_CTL_TASSEL_SMCLK (0x0200)
360 #define TIMER_CTL_TASSEL_INV_TCLK (0x0300)
361 
367 #define TIMER_CCTL_CCIFG (0x0001)
368 #define TIMER_CCTL_COV (0x0002)
369 #define TIMER_CCTL_OUT (0x0004)
370 #define TIMER_CCTL_CCI (0x0008)
371 #define TIMER_CCTL_CCIE (0x0010)
372 #define TIMER_CCTL_OUTMOD_MASK (0x00e0)
373 #define TIMER_CCTL_OUTMOD_OUTVAL (0x0000)
374 #define TIMER_CCTL_OUTMOD_SET (0x0020)
375 #define TIMER_CCTL_OUTMOD_TOG_RESET (0x0040)
376 #define TIMER_CCTL_OUTMOD_SET_RESET (0x0060)
377 #define TIMER_CCTL_OUTMOD_TOGGLE (0x0080)
378 #define TIMER_CCTL_OUTMOD_RESET (0x00a0)
379 #define TIMER_CCTL_OUTMOD_TOG_SET (0x00c0)
380 #define TIMER_CCTL_OUTMOD_RESET_SET (0x00e0)
381 #define TIMER_CCTL_CAP (0x0100)
382 #define TIMER_CCTL_CLLD_MASK (0x0600)
383 #define TIMER_CCTL_SCS (0x0800)
384 #define TIMER_CCTL_CCIS_MASK (0x3000)
385 #define TIMER_CCTL_CM_MASK (0xc000)
386 
392 #define SFR_BASE ((uint16_t)0x0000)
393 #define PORT_1_BASE ((uint16_t)0x0020)
394 #define PORT_2_BASE ((uint16_t)0x0028)
395 #define PORT_3_BASE ((uint16_t)0x0018)
396 #define PORT_4_BASE ((uint16_t)0x001c)
397 #define PORT_5_BASE ((uint16_t)0x0030)
398 #define PORT_6_BASE ((uint16_t)0x0034)
399 #define CLK_BASE ((uint16_t)0x0053)
400 #define USART_0_BASE ((uint16_t)0x0070)
401 #define USART_1_BASE ((uint16_t)0x0078)
402 #define TIMER_IVEC_BASE ((uint16_t)0x011e)
403 #define TIMER_A_BASE ((uint16_t)0x0160)
404 #define TIMER_B_BASE ((uint16_t)0x0180)
405 #define WD_BASE ((uint16_t)0x0120)
406 #define USCI_0_BASE ((uint16_t)0x005d)
407 #define USCI_0_A_BASE ((uint16_t)0x0060)
408 #define USCI_0_B_BASE ((uint16_t)0x0068)
409 #define USCI_1_BASE ((uint16_t)0x00cd)
410 #define USCI_1_A_BASE ((uint16_t)0x00d0)
411 #define USCI_1_B_BASE ((uint16_t)0x00d8)
412 
418 #define SFR ((msp_sfr_t *)SFR_BASE)
419 #define PORT_1 ((msp_port_t *)PORT_1_BASE)
420 #define PORT_2 ((msp_port_t *)PORT_2_BASE)
421 #define PORT_3 ((msp_port_t *)PORT_3_BASE)
422 #define PORT_4 ((msp_port_t *)PORT_4_BASE)
423 #define PORT_5 ((msp_port_t *)PORT_5_BASE)
424 #define PORT_6 ((msp_port_t *)PORT_6_BASE)
425 #define CLK ((msp_clk_t *)CLK_BASE)
426 #define USART_0 ((msp_usart_t *)USART_0_BASE)
427 #define USART_1 ((msp_usart_t *)USART_1_BASE)
428 #define TIMER_IVEC ((msp_timer_ivec_t *)TIMER_IVEC_BASE)
429 #define TIMER_A ((msp_timer_t *)TIMER_A_BASE)
430 #define TIMER_B ((msp_timer_t *)TIMER_B_BASE)
431 #define WD ((msp_wd_t *)WD_BASE)
432 #define USCI_0 ((msp_usci_t *)USCI_0_BASE)
433 #define USCI_1 ((msp_usci_t *)USCI_1_BASE)
434 #define USCI_0_A_SPI ((msp_usci_spi_t *)USCI_0_A_BASE)
435 #define USCI_0_B_SPI ((msp_usci_spi_t *)USCI_0_B_BASE)
436 #define USCI_1_A ((msp_usci_t *)USCI_1_A_BASE)
437 #define USCI_1_B ((msp_usci_t *)USCI_1_B_BASE)
438 
440 #ifdef __cplusplus
441 }
442 #endif
443 
444 #endif /* MSP430_REGS_H */
445 
USCI SPI specific registers.
Definition: msp430_regs.h:117
REG8 ASTAT
A status.
Definition: msp430_regs.h:101
REG8 BR1
baud rate 1
Definition: msp430_regs.h:121
REG8 AMCTL
A modulation control.
Definition: msp430_regs.h:100
REG8 IE1
interrupt enable 1
Definition: msp430_regs.h:44
REG8 IFG1
interrupt flag 1
Definition: msp430_regs.h:46
USCI universal serial control interface registers.
Definition: msp430_regs.h:92
REG8 BBR1
B baud rate 1.
Definition: msp430_regs.h:107
REG8 ARXBUF
A receive buffer.
Definition: msp430_regs.h:102
REG8 SEL
alternative function select
Definition: msp430_regs.h:59
REG16 TBIV
TIMER_A interrupt status.
Definition: msp430_regs.h:132
REG8 CTL
USART control.
Definition: msp430_regs.h:79
REG8 BI2CIE
I2C interrupt enable.
Definition: msp430_regs.h:108
REG8 IRRCTL
IrDA receive control.
Definition: msp430_regs.h:95
REG8 ACTL1
A control 1.
Definition: msp430_regs.h:97
REG8 DIR
pin direction
Definition: msp430_regs.h:68
REG8 RCTL
receive control
Definition: msp430_regs.h:81
REG8 IN
input data
Definition: msp430_regs.h:56
Digital I/O Port w/o interrupt functionality (P3-P6)
Definition: msp430_regs.h:55
REG8 CTL0
control 0
Definition: msp430_regs.h:118
REG8 ACTL0
A control 0.
Definition: msp430_regs.h:96
REG8 SEL
alternative function select
Definition: msp430_regs.h:72
Special function registers.
Definition: msp430_regs.h:43
REG8 IN
input data
Definition: msp430_regs.h:66
#define REG16
Shortcut to specify 16-bit wide registers.
Definition: msp430_regs.h:38
REG8 IFG2
interrupt flag 2
Definition: msp430_regs.h:47
REG8 IRTCTL
IrDA transmit control.
Definition: msp430_regs.h:94
REG8 DIR
pin direction
Definition: msp430_regs.h:58
REG8 IFG
interrupt flag
Definition: msp430_regs.h:69
REG8 ME1
module enable 1
Definition: msp430_regs.h:48
Timer interrupt status registers.
Definition: msp430_regs.h:131
REG8 ABCTL
auto baud rate control
Definition: msp430_regs.h:93
#define REG8
Shortcut to specify 8-bit wide registers.
Definition: msp430_regs.h:33
REG8 STAT
status
Definition: msp430_regs.h:123
REG8 BCTL1
B control 1.
Definition: msp430_regs.h:105
REG8 BR0
baud rate 0
Definition: msp430_regs.h:120
REG8 TXBUF
transmit buffer
Definition: msp430_regs.h:86
REG8 ABR0
A baud rate control 0.
Definition: msp430_regs.h:98
Digital I/O Port with interrupt functionality (P1 & P2)
Definition: msp430_regs.h:65
REG8 BCTL0
B control 0.
Definition: msp430_regs.h:104
REG8 IE
interrupt enable
Definition: msp430_regs.h:71
REG8 BTXBUF
B transmit buffer.
Definition: msp430_regs.h:111
REG8 RXBUF
receive buffer
Definition: msp430_regs.h:85
REG8 RXBUF
receive buffer
Definition: msp430_regs.h:124
REG16 TAIV
TIMER_B interrupt status.
Definition: msp430_regs.h:134
REG8 BRXBUF
B receive buffer.
Definition: msp430_regs.h:110
REG8 ABR1
A baud rate control 1.
Definition: msp430_regs.h:99
REG8 OD
output data
Definition: msp430_regs.h:67
REG8 TCTL
transmit control
Definition: msp430_regs.h:80
REG8 BR1
baud rate control 1
Definition: msp430_regs.h:84
REG8 ATXBUF
A transmit buffer.
Definition: msp430_regs.h:103
Timer module registers.
Definition: cc430_regs.h:43
REG8 BBR0
B baud rate 0.
Definition: msp430_regs.h:106
REG8 BSTAT
B status.
Definition: msp430_regs.h:109
REG8 TXBUF
transmit buffer
Definition: msp430_regs.h:125
REG8 IE2
interrupt enable 2
Definition: msp430_regs.h:45
REG8 reserved
reserved
Definition: msp430_regs.h:122
REG8 BR0
baud rate control 0
Definition: msp430_regs.h:83
REG8 MCTL
modulation control
Definition: msp430_regs.h:82
USART (UART, SPI and I2C) registers.
Definition: msp430_regs.h:78
REG8 OD
output data
Definition: msp430_regs.h:57
REG8 IES
interrupt edge select
Definition: msp430_regs.h:70
REG8 CTL1
control 1
Definition: msp430_regs.h:119
REG8 ME2
module enable 2
Definition: msp430_regs.h:49