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mrf24j40_registers.h
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1 /*
2  * Copyright (C) 2017 Neo Nenaco <neo@nenaco.de>
3  * Copyright (C) 2017 Koen Zandberg <koen@bergzand.net>
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef MRF24J40_REGISTERS_H
22 #define MRF24J40_REGISTERS_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 
33 #define MRF24J40_SHORT_ADDR_TRANS (0x00)
34 #define MRF24J40_LONG_ADDR_TRANS (0x80)
35 #define MRF24J40_ACCESS_READ (0x00)
36 #define MRF24J40_ACCESS_WRITE (0x01)
37 #define MRF24J40_ACCESS_WRITE_LNG (0x10)
38 #define MRF24J40_ADDR_OFFSET (0x01)
39 
45 #define MRF24J40_TX_NORMAL_FIFO (0x000)
46 #define MRF24J40_TX_BEACON_FIFO (0x080)
47 #define MRF24J40_TX_GTS1_FIFO (0x100)
48 #define MRF24J40_TX_GTS2_FIFO (0x180)
49 #define MRF24J40_RX_FIFO (0x300)
50 
56 #define MRF24J40_REG_RXMCR (0x00)
57 #define MRF24J40_REG_PANIDL (0x01)
58 #define MRF24J40_REG_PANIDH (0x02)
59 #define MRF24J40_REG_SADRL (0x03)
60 #define MRF24J40_REG_SADRH (0x04)
61 #define MRF24J40_REG_EADR0 (0x05)
62 #define MRF24J40_REG_EADR1 (0x06)
63 #define MRF24J40_REG_EADR2 (0x07)
64 #define MRF24J40_REG_EADR3 (0x08)
65 #define MRF24J40_REG_EADR4 (0x09)
66 #define MRF24J40_REG_EADR5 (0x0A)
67 #define MRF24J40_REG_EADR6 (0x0B)
68 #define MRF24J40_REG_EADR7 (0x0C)
69 #define MRF24J40_REG_RXFLUSH (0x0D)
70 #define MRF24J40_REG_ORDER (0x10)
71 #define MRF24J40_REG_TXMCR (0x11)
72 #define MRF24J40_REG_ACKTMOUT (0x12)
73 #define MRF24J40_REG_ESLOTG1 (0x13)
74 #define MRF24J40_REG_SYMTICKL (0x14)
75 #define MRF24J40_REG_SYMTICKH (0x15)
76 #define MRF24J40_REG_PACON0 (0x16)
77 #define MRF24J40_REG_PACON1 (0x17)
78 #define MRF24J40_REG_PACON2 (0x18)
79 #define MRF24J40_REG_TXBCON0 (0x1A)
80 #define MRF24J40_REG_TXNCON (0x1B)
81 #define MRF24J40_REG_TXG1CON (0x1C)
82 #define MRF24J40_REG_TXG2CON (0x1D)
83 #define MRF24J40_REG_ESLOTG23 (0x1E)
84 #define MRF24J40_REG_ESLOTG45 (0x1F)
85 #define MRF24J40_REG_ESLOTG67 (0x20)
86 #define MRF24J40_REG_TXPEND (0x21)
87 #define MRF24J40_REG_WAKECON (0x22)
88 #define MRF24J40_REG_FRMOFFSET (0x23)
89 #define MRF24J40_REG_TXSTAT (0x24)
90 #define MRF24J40_REG_TXBCON1 (0x25)
91 #define MRF24J40_REG_GATECLK (0x26)
92 #define MRF24J40_REG_TXTIME (0x27)
93 #define MRF24J40_REG_HSYMTMRL (0x28)
94 #define MRF24J40_REG_HSYMTMRH (0x29)
95 #define MRF24J40_REG_SOFTRST (0x2A)
96 #define MRF24J40_REG_SECCON0 (0x2C)
97 #define MRF24J40_REG_SECCON1 (0x2D)
98 #define MRF24J40_REG_TXSTBL (0x2E)
99 #define MRF24J40_REG_RXSR (0x30)
100 #define MRF24J40_REG_INTSTAT (0x31)
101 #define MRF24J40_REG_INTCON (0x32)
102 #define MRF24J40_REG_GPIO (0x33)
103 #define MRF24J40_REG_TRISGPIO (0x34)
104 #define MRF24J40_REG_SLPACK (0x35)
105 #define MRF24J40_REG_RFCTL (0x36)
106 #define MRF24J40_REG_SECCR2 (0x37)
107 #define MRF24J40_REG_BBREG0 (0x38)
108 #define MRF24J40_REG_BBREG1 (0x39)
109 #define MRF24J40_REG_BBREG2 (0x3A)
110 #define MRF24J40_REG_BBREG3 (0x3B)
111 #define MRF24J40_REG_BBREG4 (0x3C)
112 #define MRF24J40_REG_BBREG6 (0x3E)
113 #define MRF24J40_REG_CCAEDTH (0x3F)
114 
120 #define MRF24J40_REG_RFCON0 (0x200)
121 #define MRF24J40_REG_RFCON1 (0x201)
122 #define MRF24J40_REG_RFCON2 (0x202)
123 #define MRF24J40_REG_RFCON3 (0x203)
124 #define MRF24J40_REG_RFCON5 (0x205)
125 #define MRF24J40_REG_RFCON6 (0x206)
126 #define MRF24J40_REG_RFCON7 (0x207)
127 #define MRF24J40_REG_RFCON8 (0x208)
128 #define MRF24J40_REG_SLPCAL0 (0x209)
129 #define MRF24J40_REG_SLPCAL1 (0x20A)
130 #define MRF24J40_REG_SLPCAL2 (0x20B)
131 #define MRF24J40_REG_RFSTATE (0x20F)
132 #define MRF24J40_REG_RSSI (0x210)
133 #define MRF24J40_REG_SLPCON0 (0x211)
134 #define MRF24J40_REG_SLPCON1 (0x220)
135 #define MRF24J40_REG_WAKETIMEL (0x222)
136 #define MRF24J40_REG_WAKETIMEH (0x223)
137 #define MRF24J40_REG_REMCNTL (0x224)
138 #define MRF24J40_REG_REMCNTH (0x225)
139 #define MRF24J40_REG_MAINCNT0 (0x226)
140 #define MRF24J40_REG_MAINCNT1 (0x227)
141 #define MRF24J40_REG_MAINCNT2 (0x228)
142 #define MRF24J40_REG_MAINCNT3 (0x229)
143 #define MRF24J40_REG_TESTMODE (0x22F)
144 #define MRF24J40_REG_ASSOEADR0 (0x230)
145 #define MRF24J40_REG_ASSOEADR1 (0x231)
146 #define MRF24J40_REG_ASSOEADR2 (0x232)
147 #define MRF24J40_REG_ASSOEADR3 (0x233)
148 #define MRF24J40_REG_ASSOEADR4 (0x234)
149 #define MRF24J40_REG_ASSOEADR5 (0x235)
150 #define MRF24J40_REG_ASSOEADR6 (0x236)
151 #define MRF24J40_REG_ASSOEADR7 (0x237)
152 #define MRF24J40_REG_ASSOSADR0 (0x238)
153 #define MRF24J40_REG_ASSOSADR1 (0x239)
154 #define MRF24J40_REG_UPNONCE0 (0x240)
155 #define MRF24J40_REG_UPNONCE1 (0x241)
156 #define MRF24J40_REG_UPNONCE2 (0x242)
157 #define MRF24J40_REG_UPNONCE3 (0x243)
158 #define MRF24J40_REG_UPNONCE4 (0x244)
159 #define MRF24J40_REG_UPNONCE5 (0x245)
160 #define MRF24J40_REG_UPNONCE6 (0x246)
161 #define MRF24J40_REG_UPNONCE7 (0x247)
162 #define MRF24J40_REG_UPNONCE8 (0x248)
163 #define MRF24J40_REG_UPNONCE9 (0x249)
164 #define MRF24J40_REG_UPNONCE10 (0x24A)
165 #define MRF24J40_REG_UPNONCE11 (0x24B)
166 #define MRF24J40_REG_UPNONCE12 (0x24C)
167 
173 #define MRF24J40_RESET_DELAY (2000U) /* Datasheet MRF24J40 ~2ms */
174 #define MRF24J40_RESET_PULSE_WIDTH (20000U) /* 20ms (estimated */
175 
176 #define MRF24J40_WAKEUP_DELAY (2000U)
177 
178 #define MRF24J40_DELAY_SLEEP_TOGGLE (50U)
179 #define MRF24J40_STATE_RESET_DELAY (200U)
180 
186 #define MRF24J40_RXMCR_NOACKRSP (0b00100000)
187 #define MRF24J40_RXMCR_PANCOORD (0b00001000)
188 #define MRF24J40_RXMCR_COORD (0b00000100)
189 #define MRF24J40_RXMCR_ERRPKT (0b00000010)
190 #define MRF24J40_RXMCR_PROMI (0b00000001)
191 
197 #define MRF24J40_RXFLUSH_WAKEPOL (0b01000000)
198 #define MRF24J40_RXFLUSH_WAKEPAD (0b00100000)
199 #define MRF24J40_RXFLUSH_CMDONLY (0b00001000)
200 #define MRF24J40_RXFLUSH_DATAONLY (0b00000100)
201 #define MRF24J40_RXFLUSH_BCNONLY (0b00000010)
202 #define MRF24J40_RXFLUSH_RXFLUSH (0b00000001)
203 
209 #define MRF24J40_TXMCR_CSMA_BACKOFF_MASK (0x07)
210 
211 #define MRF24J40_TXMCR_MACMINBE (0b00011000)
212 #define MRF24J40_TXMCR_NOCSMA (0b10000000)
213 #define MRF24J40_TXMCR_BATLIFEXT (0b01000000)
214 #define MRF24J40_TXMCR_SLOTTED (0b00100000)
215 #define MRF24J40_TXMCR_MACMINBE1 (0b00010000)
216 #define MRF24J40_TXMCR_MACMINBE0 (0b00001000)
217 #define MRF24J40_TXMCR_CSMABF2 (0b00000100)
218 #define MRF24J40_TXMCR_CSMABF1 (0b00000010)
219 #define MRF24J40_TXMCR_CSMABF0 (0b00000001)
220 
227 #define MRF24J40_PACON2_FIFOEN (0b10000000)
228 #define MRF24J40_PACON2_TXONTS3 (0b00100000)
229 #define MRF24J40_PACON2_TXONTS2 (0b00010000)
230 #define MRF24J40_PACON2_TXONTS1 (0b00001000)
231 #define MRF24J40_PACON2_TXONTS0 (0b00000100)
232 #define MRF24J40_PACON2_TXONT8 (0b00000010)
233 #define MRF24J40_PACON2_TXONT7 (0b00000001)
234 
240 #define MRF24J40_TXNCON_FPSTAT (0x10)
241 #define MRF24J40_TXNCON_INDIRECT (0x08)
242 #define MRF24J40_TXNCON_TXNACKREQ (0x04)
243 #define MRF24J40_TXNCON_TXNSECEN (0x02)
244 #define MRF24J40_TXNCON_TXNTRIG (0x01)
245 
251 #define MRF24J40_WAKECON_IMMWAKE (0b10000000)
252 #define MRF24J40_WAKECON_REGWAKE (0b01000000)
253 
259 #define MRF24J40_TXSTAT_MAX_FRAME_RETRIES (0b11000000)
260 #define MRF24J40_TXSTAT_TXNRETRY1 (0b10000000)
261 #define MRF24J40_TXSTAT_TXNRETRY0 (0b01000000)
262 #define MRF24J40_TXSTAT_CCAFAIL (0b00100000)
263 #define MRF24J40_TXSTAT_TXG2FNT (0b00010000)
264 #define MRF24J40_TXSTAT_TXG1FNT (0b00001000)
265 #define MRF24J40_TXSTAT_TXG2STAT (0b00000100)
266 #define MRF24J40_TXSTAT_TXG1STAT (0b00000010)
267 #define MRF24J40_TXSTAT_TXNSTAT (0b00000001)
268 
274 #define MRF24J40_SOFTRST_RSTPWR (0b00000100)
275 #define MRF24J40_SOFTRST_RSTBB (0b00000010)
276 #define MRF24J40_SOFTRST_RSTMAC (0b00000001)
277 
283 #define MRF24J40_TXSTBL_RFSTBL3 (0x80)
284 #define MRF24J40_TXSTBL_RFSTBL2 (0x40)
285 #define MRF24J40_TXSTBL_RFSTBL1 (0x20)
286 #define MRF24J40_TXSTBL_RFSTBL0 (0x10)
287 #define MRF24J40_TXSTBL_MSIFS3 (0x08)
288 #define MRF24J40_TXSTBL_MSIFS2 (0x04)
289 #define MRF24J40_TXSTBL_MSIFS1 (0x02)
290 #define MRF24J40_TXSTBL_MSIFS0 (0x01)
291 
297 #define MRF24J40_INTSTAT_SLPIF (0x80)
298 #define MRF24J40_INTSTAT_WAKEIF (0x40)
299 #define MRF24J40_INTSTAT_HSYMTMRIF (0x20)
300 #define MRF24J40_INTSTAT_SECIF (0x10)
301 #define MRF24J40_INTSTAT_RXIF (0x08)
302 #define MRF24J40_INTSTAT_TXG2IF (0x04)
303 #define MRF24J40_INTSTAT_TXG1IF (0x02)
304 #define MRF24J40_INTSTAT_TXNIF (0x01)
305 
311 #define MRF24J40_INTCON_SLPIE (0x80)
312 #define MRF24J40_INTCON_WAKEIE (0x40)
313 #define MRF24J40_INTCON_HSYMTMRIE (0x20)
314 #define MRF24J40_INTCON_SECIE (0x10)
315 #define MRF24J40_INTCON_RXIE (0x08)
316 #define MRF24J40_INTCON_TXG2IE (0x04)
317 #define MRF24J40_INTCON_TXG1IE (0x02)
318 #define MRF24J40_INTCON_TXNIE (0x01)
319 
325 #define MRF24J40_SLPACK_SLPACK (0b10000000)
326 
332 #define MRF24J40_RFCTL_WAKECNT8 (0x10)
333 #define MRF24J40_RFCTL_WAKECNT7 (0x08)
334 #define MRF24J40_RFCTL_RFRST (0x04)
335 #define MRF24J40_RFCTL_RFTXMODE (0x02)
336 #define MRF24J40_RFCTL_RFRXMODE (0x01)
337 
343 #define MRF24J40_BBREG1_RXDECINV (0b00000100)
344 
350 #define MRF24J40_BBREG2_CCAMODE3 (0b11000000)
351 #define MRF25J40_BBREG2_CCAMODE1 (0b10000000)
352 #define MRF24J40_BBREG2_CCAMODE2 (0b01000000)
353 
354 #define MRF24J40_BBREG2_CCACSTH (0b00111100)
355 
361 #define MRF24J40_BBREG6_RSSIMODE1 (0b10000000)
362 #define MRF24J40_BBREG6_RSSIMODE2 (0b01000000)
363 #define MRF24J40_BBREG2_RSSIRDY (0b00000001)
364 
365 #define MRF24J40_BBREG2_CCACSTH (0b00111100)
366 
372 #define MRF24J40_RFCON1_VCOOPT7 (0x80)
373 #define MRF24J40_RFCON1_VCOOPT6 (0x40)
374 #define MRF24J40_RFCON1_VCOOPT5 (0x20)
375 #define MRF24J40_RFCON1_VCOOPT4 (0x10)
376 #define MRF24J40_RFCON1_VCOOPT3 (0x08)
377 #define MRF24J40_RFCON1_VCOOPT2 (0x04)
378 #define MRF24J40_RFCON1_VCOOPT1 (0x02)
379 #define MRF24J40_RFCON1_VCOOPT0 (0x01)
380 
386 #define MRF24J40_RFCON2_PLLEN (0x80)
387 
393 #define MRF24J40_RFCON6_TXFIL (0x80)
394 #define MRF24J40_RFCON6_20MRECVR (0x10)
395 #define MRF24J40_RFCON6_BATEN (0x08)
396 
402 #define MRF24J40_RFCON7_SLPCLKSEL1 (0x80)
403 #define MRF24J40_RFCON7_SLPCLKSEL2 (0x40)
404 
410 #define MRF24J40_RFCON8_RFVCO (0x10)
411 
417 #define MRF24J40_RFSTATE_MASK (0xA0)
418 #define MRF24J40_RFSTATE_RTSEL2 (0xE0)
419 #define MRF24J40_RFSTATE_RTSEL1 (0xC0)
420 #define MRF24J40_RFSTATE_RX (0xA0)
421 #define MRF24J40_RFSTATE_TX (0x80)
422 #define MRF24J40_RFSTATE_CALVCO (0x60)
423 #define MRF24J40_RFSTATE_SLEEP (0x40)
424 #define MRF24J40_RFSTATE_CALFIL (0x20)
425 #define MRF24J40_RFSTATE_RESET (0x00)
426 
432 #define MRF24J40_SLPCON0_INTEDGE (0x02)
433 #define MRF24J40_SLPCON0_SLPCLKEN (0x01)
434 
440 #define MRF24J40_SLPCON1_CLKOUTEN (0x20)
441 #define MRF24J40_SLPCON1_SLPCLKDIV4 (0x10)
442 #define MRF24J40_SLPCON1_SLPCLKDIV3 (0x08)
443 #define MRF24J40_SLPCON1_SLPCLKDIV2 (0x04)
444 #define MRF24J40_SLPCON1_SLPCLKDIV1 (0x02)
445 #define MRF24J40_SLPCON1_SLPCLKDIV0 (0x01)
446 
449 #ifdef __cplusplus
450 }
451 #endif
452 
453 #endif /* MRF24J40_REGISTERS_H */
454