mpl3115a2_reg.h
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1 /*
2  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  *
8  */
9 
21 #ifndef MPL3115A2_REG_H
22 #define MPL3115A2_REG_H
23 
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
29 #define MPL3115A2_STATUS 0x00
30 #define MPL3115A2_OUT_P_MSB 0x01
31 #define MPL3115A2_OUT_P_CSB 0x02
32 #define MPL3115A2_OUT_P_LSB 0x03
33 #define MPL3115A2_OUT_T_MSB 0x04
34 #define MPL3115A2_OUT_T_LSB 0x05
35 #define MPL3115A2_DR_STATUS 0x06
36 #define MPL3115A2_OUT_P_DELTA MSB 0x07
37 #define MPL3115A2_OUT_P_DELTA_CSB 0x08
38 #define MPL3115A2_OUT_P_DELTA_LSB 0x09
39 #define MPL3115A2_OUT_T_DELTA_MSB 0x0A
40 #define MPL3115A2_OUT_T_DELTA_LSB 0x0B
41 #define MPL3115A2_WHO_AM_I 0x0C
42 #define MPL3115A2_F_STATUS 0x0D
43 #define MPL3115A2_F_DATA 0x0E
44 #define MPL3115A2_F_SETUP 0x0F
45 #define MPL3115A2_TIME_DLY 0x10
46 #define MPL3115A2_SYSMOD 0x11
47 #define MPL3115A2_INT_SOURCE 0x12
48 #define MPL3115A2_PT_DATA_CFG 0x13
49 #define MPL3115A2_BAR_IN_MSB 0x14
50 #define MPL3115A2_BAR_IN_LSB 0x15
51 #define MPL3115A2_P_TGT_MSB 0x16
52 #define MPL3115A2_P_TGT_LSB 0x17
53 #define MPL3115A2_T_TGT 0x18
54 #define MPL3115A2_P_WND_MSB 0x19
55 #define MPL3115A2_P_WND_LSB 0x1A
56 #define MPL3115A2_T_WND 0x1B
57 #define MPL3115A2_P_MIN_MSB 0x1C
58 #define MPL3115A2_P_MIN_CSB 0x1D
59 #define MPL3115A2_P_MIN_LSB 0x1E
60 #define MPL3115A2_T_MIN_MSB 0x1F
61 #define MPL3115A2_T_MIN_LSB 0x20
62 #define MPL3115A2_P_MAX_MSB 0x21
63 #define MPL3115A2_P_MAX_CSB 0x22
64 #define MPL3115A2_P_MAX_LSB 0x23
65 #define MPL3115A2_T_MAX_MSB 0x24
66 #define MPL3115A2_T_MAX_LSB 0x25
67 #define MPL3115A2_CTRL_REG1 0x26
68 #define MPL3115A2_CTRL_REG2 0x27
69 #define MPL3115A2_CTRL_REG3 0x28
70 #define MPL3115A2_CTRL_REG4 0x29
71 #define MPL3115A2_CTRL_REG5 0x2A
72 #define MPL3115A2_OFF_P 0x2B
73 #define MPL3115A2_OFF_T 0x2C
74 #define MPL3115A2_OFF_H 0x2D
76 #define MPL3115A2_STATUS_TDR (1 << 1)
77 #define MPL3115A2_STATUS_PDR (1 << 2)
78 #define MPL3115A2_STATUS_PTDR (1 << 3)
79 #define MPL3115A2_STATUS_TOW (1 << 5)
80 #define MPL3115A2_STATUS_POW (1 << 6)
81 #define MPL3115A2_STATUS_PTOW (1 << 7)
82 
83 #define MPL3115A2_PT_DATA_CFG_TDEFE (1 << 0)
84 #define MPL3115A2_PT_DATA_CFG_PDEFE (1 << 1)
85 #define MPL3115A2_PT_DATA_CFG_DREM (1 << 2)
86 
87 #define MPL3115A2_CTRL_REG1_SBYB (1 << 0)
88 #define MPL3115A2_CTRL_REG1_OST (1 << 1)
89 #define MPL3115A2_CTRL_REG1_RST (1 << 2)
90 #define MPL3115A2_CTRL_REG1_OS_SHIFT 3
91 #define MPL3115A2_CTRL_REG1_OS_MASK 0x38
92 #define MPL3115A2_CTRL_REG1_OS(x) (((uint8_t)(((uint8_t)(x))<<MPL3115A2_CTRL_REG1_OS_SHIFT))\
93  &MPL3115A2_CTRL_REG1_OS_MASK)
94 #define MPL3115A2_CTRL_REG1_RAW (1 << 6)
95 #define MPL3115A2_CTRL_REG1_ALT (1 << 7)
96 
97 #define MPL3115A2_CTRL_REG2_ST_SHIFT 0
98 #define MPL3115A2_CTRL_REG2_ST_MASK 0xF
99 #define MPL3115A2_CTRL_REG2_ST(x) (((uint8_t)(((uint8_t)(x))<<MPL3115A2_CTRL_REG2_ST_SHIFT))\
100  &MPL3115A2_CTRL_REG2_ST_MASK)
101 #define MPL3115A2_CTRL_REG2_ALARM_SEL (1 << 4)
102 #define MPL3115A2_CTRL_REG2_LOAD_OPUT (1 << 5)
103 
104 #define MPL3115A2_CTRL_REG3_PP_OD2 (1 << 0)
105 #define MPL3115A2_CTRL_REG3_IPOL2 (1 << 1)
106 #define MPL3115A2_CTRL_REG3_PP_OD1 (1 << 4)
107 #define MPL3115A2_CTRL_REG3_IPOL1 (1 << 5)
108 
109 #define MPL3115A2_CTRL_REG4_INT_EN_TCHG (1 << 0)
110 #define MPL3115A2_CTRL_REG4_INT_EN_PCHG (1 << 1)
111 #define MPL3115A2_CTRL_REG4_INT_EN_TTH (1 << 2)
112 #define MPL3115A2_CTRL_REG4_INT_EN_PTH (1 << 3)
113 #define MPL3115A2_CTRL_REG4_INT_EN_TW (1 << 4)
114 #define MPL3115A2_CTRL_REG4_INT_EN_PW (1 << 5)
115 #define MPL3115A2_CTRL_REG4_INT_EN_FIFO (1 << 6)
116 #define MPL3115A2_CTRL_REG4_INT_EN_DRDY (1 << 7)
117 
118 #define MPL3115A2_CTRL_REG5_INT_TCHG (1 << 0)
119 #define MPL3115A2_CTRL_REG5_INT_PCHG (1 << 1)
120 #define MPL3115A2_CTRL_REG5_INT_TTH (1 << 2)
121 #define MPL3115A2_CTRL_REG5_INT_PTH (1 << 3)
122 #define MPL3115A2_CTRL_REG5_INT_TW (1 << 4)
123 #define MPL3115A2_CTRL_REG5_INT_PW (1 << 5)
124 #define MPL3115A2_CTRL_REG5_INT_FIFO (1 << 6)
125 #define MPL3115A2_CTRL_REG5_INT_DRDY (1 << 7)
126 
127 #define MPL3115A2_ID 0xC4
129 #ifdef __cplusplus
130 }
131 #endif
132 
133 #endif
134