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mma8x5x_regs.h
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1 /*
2  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
3  * 2016 Freie Universit├Ąt Berlin
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  *
9  */
10 
23 #ifndef MMA8X5X_REG_H
24 #define MMA8X5X_REG_H
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
35 #define MMA8X5X_STATUS 0x00
36 #define MMA8X5X_OUT_X_MSB 0x01
37 #define MMA8X5X_OUT_X_LSB 0x02
38 #define MMA8X5X_OUT_Y_MSB 0x03
39 #define MMA8X5X_OUT_Y_LSB 0x04
40 #define MMA8X5X_OUT_Z_MSB 0x05
41 #define MMA8X5X_OUT_Z_LSB 0x06
42 #define MMA8X5X_F_SETUP 0x09
43 #define MMA8X5X_TRIG_CFG 0x0A
44 #define MMA8X5X_SYSMOD 0x0B
45 #define MMA8X5X_INT_SOURCE 0x0C
46 #define MMA8X5X_WHO_AM_I 0x0D
47 #define MMA8X5X_XYZ_DATA_CFG 0x0E
48 #define MMA8X5X_HP_FILTER_CUTOFF 0x0F
49 #define MMA8X5X_PL_STATUS 0x10
50 #define MMA8X5X_PL_CFG 0x11
51 #define MMA8X5X_PL_COUNT 0x12
52 #define MMA8X5X_PL_BF_ZCOMP 0x13
53 #define MMA8X5X_P_L_THS_REG 0x14
54 #define MMA8X5X_FF_MT_CFG 0x15
55 #define MMA8X5X_FF_MT_SRC 0x16
56 #define MMA8X5X_FF_MT_THS 0x17
57 #define MMA8X5X_FF_MT_COUNT 0x18
58 #define MMA8X5X_TRANSIENT_CFG 0x1D
59 #define MMA8X5X_TRANSIENT_SRC 0x1E
60 #define MMA8X5X_TRANSIENT_THS 0x1F
61 #define MMA8X5X_TRANSIENT_COUNT 0x20
62 #define MMA8X5X_PULSE_CFG 0x21
63 #define MMA8X5X_PULSE_SRC 0x22
64 #define MMA8X5X_PULSE_THSX 0x23
65 #define MMA8X5X_PULSE_THSY 0x24
66 #define MMA8X5X_PULSE_THSZ 0x25
67 #define MMA8X5X_PULSE_TMLT 0x26
68 #define MMA8X5X_PULSE_LTCY 0x27
69 #define MMA8X5X_PULSE_WIND 0x28
70 #define MMA8X5X_ASLP_COUNT 0x29
71 #define MMA8X5X_CTRL_REG1 0x2A
72 #define MMA8X5X_CTRL_REG2 0x2B
73 #define MMA8X5X_CTRL_REG3 0x2C
74 #define MMA8X5X_CTRL_REG4 0x2D
75 #define MMA8X5X_CTRL_REG5 0x2E
76 #define MMA8X5X_OFF_X 0x2F
77 #define MMA8X5X_OFF_Y 0x30
78 #define MMA8X5X_OFF_Z 0x31
85 #define MMA8X5X_STATUS_XDR (1 << 0)
86 #define MMA8X5X_STATUS_YDR (1 << 1)
87 #define MMA8X5X_STATUS_ZDR (1 << 2)
88 #define MMA8X5X_STATUS_ZYXDR (1 << 3)
89 #define MMA8X5X_STATUS_XOW (1 << 4)
90 #define MMA8X5X_STATUS_YOW (1 << 5)
91 #define MMA8X5X_STATUS_ZOW (1 << 6)
92 #define MMA8X5X_STATUS_ZYXOW (1 << 7)
93 
94 #define MMA8X5X_F_STATUS_F_CNT_MASK 0x3F
95 #define MMA8X5X_F_STATUS_F_WMRK_FLAG (1 << 6)
96 #define MMA8X5X_F_STATUS_F_OVF (1 << 7)
97 
98 #define MMA8X5X_F_SETUP_MODE_MASK 0xC0
99 #define MMA8X5X_F_SETUP_MODE_DISABLED 0
100 #define MMA8X5X_F_SETUP_MODE_CIRCULAR 1
101 #define MMA8X5X_F_SETUP_MODE_STOP 2
102 #define MMA8X5X_F_SETUP_MODE_TRIGGER 3
103 #define MMA8X5X_F_SETUP_F_WMRK_MASK 0x3F
104 
105 #define MMA8X5X_TRIG_CFG_FF_MT (1 << 2)
106 #define MMA8X5X_TRIG_CFG_PULSE (1 << 3)
107 #define MMA8X5X_TRIG_CFG_LNDPRT (1 << 4)
108 #define MMA8X5X_TRIG_CFG_TRANS (1 << 5)
109 
110 #define MMA8X5X_SYSMOD_MASK 0x3
111 #define MMA8X5X_SYSMOD_STANDBY 0
112 #define MMA8X5X_SYSMOD_WAKE 1
113 #define MMA8X5X_SYSMOD_SLEEP 2
114 #define MMA8X5X_SYSMOD_FGT_MASK 0x7C
115 #define MMA8X5X_SYSMOD_FGERR (1 << 7)
116 
117 #define MMA8X5X_INT_SOURCE_DRDY (1 << 0)
118 #define MMA8X5X_INT_SOURCE_FF_MT (1 << 2)
119 #define MMA8X5X_INT_SOURCE_PULSE (1 << 3)
120 #define MMA8X5X_INT_SOURCE_LNDPRT (1 << 4)
121 #define MMA8X5X_INT_SOURCE_TRANS (1 << 5)
122 #define MMA8X5X_INT_SOURCE_FIFO (1 << 6)
123 #define MMA8X5X_INT_SOURCE_ASLP (1 << 7)
124 
125 #define MMA8X5X_XYZ_DATA_CFG_FS_MASK 0x3
126 #define MMA8X5X_XYZ_DATA_CFG_HPF_OUT (1 << 4)
127 
128 #define MMA8X5X_HP_FILTER_SEL_MASK 0x03
129 #define MMA8X5X_HP_FILTER_LPF_EN (1 << 4)
130 #define MMA8X5X_HP_FILTER_HPF_BYP (1 << 5)
131 
132 #define MMA8X5X_PL_STATUS_BAFRO (1 << 0)
133 #define MMA8X5X_PL_STATUS_LAPO_MASK 0x6
134 #define MMA8X5X_PL_STATUS_LAPO_P_UP 0
135 #define MMA8X5X_PL_STATUS_LAPO_P_DOWN 1
136 #define MMA8X5X_PL_STATUS_LAPO_L_RIGHT 2
137 #define MMA8X5X_PL_STATUS_LAPO_L_LEFT 3
138 #define MMA8X5X_PL_STATUS_LO (1 << 6)
139 #define MMA8X5X_PL_STATUS_NEWLP (1 << 7)
140 
141 #define MMA8X5X_PL_CFG_PL_EN (1 << 6)
142 #define MMA8X5X_PL_CFG_DBCNTM (1 << 7)
143 
144 #define MMA8X5X_PL_BF_ZCOMP_ZLOCK_MASK 0x07
145 #define MMA8X5X_PL_BF_ZCOMP_BKFR_MASK 0xC0
146 
147 #define MMA8X5X_P_L_HYS_MASK 0x07
148 #define MMA8X5X_P_L_THS_MASK 0xF8
149 
150 #define MMA8X5X_FF_MT_CFG_XEFE (1 << 3)
151 #define MMA8X5X_FF_MT_CFG_YEFE (1 << 4)
152 #define MMA8X5X_FF_MT_CFG_ZEFE (1 << 5)
153 #define MMA8X5X_FF_MT_CFG_OAE (1 << 6)
154 #define MMA8X5X_FF_MT_CFG_ELE (1 << 7)
155 
156 #define MMA8X5X_FF_MT_SRC_XHP (1 << 0)
157 #define MMA8X5X_FF_MT_SRC_XHE (1 << 1)
158 #define MMA8X5X_FF_MT_SRC_YHP (1 << 2)
159 #define MMA8X5X_FF_MT_SRC_YHE (1 << 3)
160 #define MMA8X5X_FF_MT_SRC_ZHP (1 << 4)
161 #define MMA8X5X_FF_MT_SRC_ZHE (1 << 5)
162 #define MMA8X5X_FF_MT_SRC_EA (1 << 7)
163 
164 #define MMA8X5X_FF_MT_THS_MASK 0x7F
165 #define MMA8X5X_FF_MT_THS_DBCNTM (1 << 7)
166 
167 #define MMA8X5X_TRANSIENT_CFG_HPF_BYP (1 << 0)
168 #define MMA8X5X_TRANSIENT_CFG_XTEFE (1 << 1)
169 #define MMA8X5X_TRANSIENT_CFG_YTEFE (1 << 2)
170 #define MMA8X5X_TRANSIENT_CFG_ZTEFE (1 << 3)
171 #define MMA8X5X_TRANSIENT_CFG_ELE (1 << 4)
172 
173 #define MMA8X5X_TRANSIENT_SRC_XTPOL (1 << 0)
174 #define MMA8X5X_TRANSIENT_SRC_XTEVENT (1 << 1)
175 #define MMA8X5X_TRANSIENT_SRC_YTPOL (1 << 2)
176 #define MMA8X5X_TRANSIENT_SRC_YTEVENT (1 << 3)
177 #define MMA8X5X_TRANSIENT_SRC_ZTPOL (1 << 4)
178 #define MMA8X5X_TRANSIENT_SRC_ZTEVENT (1 << 5)
179 #define MMA8X5X_TRANSIENT_SRC_EA (1 << 6)
180 
181 #define MMA8X5X_TRANSIENT_THS_MASK 0x7F
182 #define MMA8X5X_TRANSIENT_THS_DBCNTM (1<< 7)
183 
184 #define MMA8X5X_PULSE_CFG_XSPEFE (1 << 0)
185 #define MMA8X5X_PULSE_CFG_XDPEFE (1 << 1)
186 #define MMA8X5X_PULSE_CFG_YSPEFE (1 << 2)
187 #define MMA8X5X_PULSE_CFG_YDPEFE (1 << 3)
188 #define MMA8X5X_PULSE_CFG_ZSPEFE (1 << 4)
189 #define MMA8X5X_PULSE_CFG_ZDPEFE (1 << 5)
190 #define MMA8X5X_PULSE_CFG_ELE (1 << 6)
191 #define MMA8X5X_PULSE_CFG_DPA (1 << 7)
192 
193 #define MMA8X5X_PULSE_SRC_POLX (1 << 0)
194 #define MMA8X5X_PULSE_SRC_POLY (1 << 1)
195 #define MMA8X5X_PULSE_SRC_POLZ (1 << 2)
196 #define MMA8X5X_PULSE_SRC_DPE (1 << 3)
197 #define MMA8X5X_PULSE_SRC_AXX (1 << 4)
198 #define MMA8X5X_PULSE_SRC_AXY (1 << 5)
199 #define MMA8X5X_PULSE_SRC_AXZ (1 << 6)
200 #define MMA8X5X_PULSE_SRC_EA (1 << 7)
201 
202 #define MMA8X5X_PULSE_THSX_MASK 0x7F
203 #define MMA8X5X_PULSE_THSY_MASK 0x7F
204 #define MMA8X5X_PULSE_THSZ_MASK 0x7F
205 
206 #define MMA8X5X_CTRL_REG1_ACTIVE (1 << 0)
207 #define MMA8X5X_CTRL_REG1_F_READ (1 << 1)
208 #define MMA8X5X_CTRL_REG1_DR_MASK 0x38
209 #define MMA8X5X_CTRL_REG1_DR_SHIFT 3
210 #define MMA8X5X_CTRL_REG1_DR(x) (((uint8_t)(((uint8_t)(x))<<MMA8X5X_CTRL_REG1_DR_SHIFT))\
211  &MMA8X5X_CTRL_REG1_DR_MASK)
212 #define MMA8X5X_CTRL_REG1_ASR_MASK 0xC0
213 #define MMA8X5X_CTRL_REG1_ASR_50HZ 0
214 #define MMA8X5X_CTRL_REG1_ASR_12HZ5 1
215 #define MMA8X5X_CTRL_REG1_ASR_6HZ25 2
216 #define MMA8X5X_CTRL_REG1_ASR_1HZ56 3
217 
218 #define MMA8X5X_CTRL_REG2_MODS_MASK 0x3
219 #define MMA8X5X_CTRL_REG2_MODS_NORMAL 0
220 #define MMA8X5X_CTRL_REG2_MODS_LNLP 1
221 #define MMA8X5X_CTRL_REG2_MODS_HR 2
222 #define MMA8X5X_CTRL_REG2_MODS_LP 3
223 #define MMA8X5X_CTRL_REG2_SLPE (1 << 2)
224 #define MMA8X5X_CTRL_REG2_SMODS_MASK 0x18
225 #define MMA8X5X_CTRL_REG2_SMODS_NORMAL 0
226 #define MMA8X5X_CTRL_REG2_SMODS_LNLP 1
227 #define MMA8X5X_CTRL_REG2_SMODS_HR 2
228 #define MMA8X5X_CTRL_REG2_SMODS_LP 3
229 #define MMA8X5X_CTRL_REG2_RST (1 << 6)
230 #define MMA8X5X_CTRL_REG2_ST (1 << 7)
231 
232 #define MMA8X5X_CTRL_REG3_PP_OD (1 << 0)
233 #define MMA8X5X_CTRL_REG3_IPOL (1 << 1)
234 #define MMA8X5X_CTRL_REG3_WAKE_FF_MT (1 << 3)
235 #define MMA8X5X_CTRL_REG3_WAKE_PULSE (1 << 4)
236 #define MMA8X5X_CTRL_REG3_WAKE_LNDPRT (1 << 5)
237 #define MMA8X5X_CTRL_REG3_WAKE_TRANS (1 << 6)
238 #define MMA8X5X_CTRL_REG3_FIFO_GATE (1 << 7)
239 
240 #define MMA8X5X_CTRL_REG4_INT_EN_DRDY (1 << 0)
241 #define MMA8X5X_CTRL_REG4_INT_EN_FF_MT (1 << 2)
242 #define MMA8X5X_CTRL_REG4_INT_EN_PULSE (1 << 3)
243 #define MMA8X5X_CTRL_REG4_INT_EN_LNDPRT (1 << 4)
244 #define MMA8X5X_CTRL_REG4_INT_EN_TRANS (1 << 5)
245 #define MMA8X5X_CTRL_REG4_INT_EN_FIFO (1 << 6)
246 #define MMA8X5X_CTRL_REG4_INT_EN_ASLP (1 << 7)
247 
248 #define MMA8X5X_CTRL_REG5_INT_CFG_DRDY (1 << 0)
249 #define MMA8X5X_CTRL_REG5_INT_CFG_FF_MT (1 << 2)
250 #define MMA8X5X_CTRL_REG5_INT_CFG_PULSE (1 << 3)
251 #define MMA8X5X_CTRL_REG5_INT_CFG_LNDPRT (1 << 4)
252 #define MMA8X5X_CTRL_REG5_INT_CFG_TRANS (1 << 5)
253 #define MMA8X5X_CTRL_REG5_INT_CFG_FIFO (1 << 6)
254 #define MMA8X5X_CTRL_REG5_INT_CFG_ASLP (1 << 7)
255 
257 #ifdef __cplusplus
258 }
259 #endif
260 
261 #endif
262