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lsm303dlhc-internal.h
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1/*
2 * Copyright (C) 2014 Freie Universität Berlin
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
20#ifndef LSM303DLHC_INTERNAL_H
21#define LSM303DLHC_INTERNAL_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
31#define LSM303DLHC_REG_CTRL1_A (0x20)
32#define LSM303DLHC_REG_CTRL2_A (0x21)
33#define LSM303DLHC_REG_CTRL3_A (0x22)
34#define LSM303DLHC_REG_CTRL4_A (0x23)
35#define LSM303DLHC_REG_CTRL5_A (0x24)
36#define LSM303DLHC_REG_CTRL6_A (0x25)
37#define LSM303DLHC_REG_REFERENCE_A (0x26)
38#define LSM303DLHC_REG_STATUS_A (0x27)
39#define LSM303DLHC_REG_OUT_X_L_A (0x28)
40#define LSM303DLHC_REG_OUT_X_H_A (0x29)
41#define LSM303DLHC_REG_OUT_Y_L_A (0x2a)
42#define LSM303DLHC_REG_OUT_Y_H_A (0x2b)
43#define LSM303DLHC_REG_OUT_Z_L_A (0x2c)
44#define LSM303DLHC_REG_OUT_Z_H_A (0x2d)
51#define LSM303DLHC_CTRL1_A_XEN (0x01)
52#define LSM303DLHC_CTRL1_A_YEN (0x02)
53#define LSM303DLHC_CTRL1_A_ZEN (0x04)
54#define LSM303DLHC_CTRL1_A_LOW_POWER (0x08)
55#define LSM303DLHC_CTRL1_A_POWEROFF (0x00)
56#define LSM303DLHC_CTRL1_A_1HZ (0x10)
57#define LSM303DLHC_CTRL1_A_10HZ (0x20)
58#define LSM303DLHC_CTRL1_A_25HZ (0x30)
59#define LSM303DLHC_CTRL1_A_50HZ (0x40)
60#define LSM303DLHC_CTRL1_A_100HZ (0x50)
61#define LSM303DLHC_CTRL1_A_200HZ (0x60)
62#define LSM303DLHC_CTRL1_A_400HZ (0x70)
63#define LSM303DLHC_CTRL1_A_1620HZ (0x80)
64#define LSM303DLHC_CTRL1_A_N1344HZ_L5376HZ (0x90)
71#define LSM303DLHC_CTRL3_A_I1_CLICK (0x80)
72#define LSM303DLHC_CTRL3_A_I1_AOI1 (0x40)
73#define LSM303DLHC_CTRL3_A_I1_AOI2 (0x20)
74#define LSM303DLHC_CTRL3_A_I1_DRDY1 (0x10)
75#define LSM303DLHC_CTRL3_A_I1_DRDY2 (0x80)
76#define LSM303DLHC_CTRL3_A_I1_WTM (0x40)
77#define LSM303DLHC_CTRL3_A_I1_OVERRUN (0x20)
78#define LSM303DLHC_CTRL3_A_I1_NONE (0x00)
85#define LSM303DLHC_CTRL4_A_BDU (0x80)
86#define LSM303DLHC_CTRL4_A_BLE (0x40)
87#define LSM303DLHC_CTRL4_A_SCALE_2G (0x00)
88#define LSM303DLHC_CTRL4_A_SCALE_4G (0x10)
89#define LSM303DLHC_CTRL4_A_SCALE_8G (0x20)
90#define LSM303DLHC_CTRL4_A_SCALE_16G (0x30)
91#define LSM303DLHC_CTRL4_A_HR (0x04)
98#define LSM303DLHC_STATUS_ZYXOR (0x80)
99#define LSM303DLHC_STATUS_ZOR (0x40)
100#define LSM303DLHC_STATUS_YOR (0x20)
101#define LSM303DLHC_STATUS_XOR (0x10)
102#define LSM303DLHC_STATUS_ZYXDA (0x08)
103#define LSM303DLHC_STATUS_ZDA (0x04)
104#define LSM303DLHC_STATUS_YDA (0x02)
105#define LSM303DLHC_STATUS_XDA (0x01)
112#define LSM303DLHC_REG_CTRL5_A_BOOT (0x80)
113#define LSM303DLHC_REG_CTRL5_A_FIFO_EN (0x40)
120#define LSM303DLHC_REG_CRA_M (0x00)
121#define LSM303DLHC_REG_CRB_M (0x01)
122#define LSM303DLHC_REG_MR_M (0x02)
123#define LSM303DLHC_REG_OUT_X_H_M (0x03)
124#define LSM303DLHC_REG_OUT_X_L_M (0x04)
125#define LSM303DLHC_REG_OUT_Y_H_M (0x05)
126#define LSM303DLHC_REG_OUT_Y_L_M (0x06)
127#define LSM303DLHC_REG_OUT_Z_H_M (0x07)
128#define LSM303DLHC_REG_OUT_Z_L_M (0x08)
129#define LSM303DLHC_REG_SR_M (0x09)
130#define LSM303DLHC_REG_TEMP_OUT_L (0x32)
131#define LSM303DLHC_REG_TEMP_OUT_H (0x31)
138#define LSM303DLHC_TEMP_EN (0x80)
139#define LSM303DLHC_TEMP_DIS (0x00)
140
141#define LSM303DLHC_TEMP_SAMPLE_0_75HZ (0x00)
142#define LSM303DLHC_TEMP_SAMPLE_1_5HZ (0x04)
143#define LSM303DLHC_TEMP_SAMPLE_3HZ (0x08)
144#define LSM303DLHC_TEMP_SAMPLE_7_5HZ (0x0c)
145#define LSM303DLHC_TEMP_SAMPLE_15HZ (0x10)
146#define LSM303DLHC_TEMP_SAMPLE_30HZ (0x14)
147#define LSM303DLHC_TEMP_SAMPLE_75HZ (0x18)
148#define LSM303DLHC_TEMP_SAMPLE_220HZ (0x1c)
155#define LSM303DLHC_GAIN_1 (0x20)
156#define LSM303DLHC_GAIN_2 (0x40)
157#define LSM303DLHC_GAIN_3 (0x60)
158#define LSM303DLHC_GAIN_4 (0x80)
159#define LSM303DLHC_GAIN_5 (0xa0)
160#define LSM303DLHC_GAIN_6 (0xc0)
161#define LSM303DLHC_GAIN_7 (0xe0)
168#define LSM303DLHC_MAG_MODE_CONTINUOUS (0x00)
169#define LSM303DLHC_MAG_MODE_SINGLE (0x01)
170#define LSM303DLHC_MAG_MODE_SLEEP (0x02)
173#ifdef __cplusplus
174}
175#endif
176
177#endif /* LSM303DLHC_INTERNAL_H */