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periph_conf_common.h
Go to the documentation of this file.
1/*
2 * Copyright (C) 2017 Eistec AB
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser General
5 * Public License v2.1. See the file LICENSE in the top level directory for more
6 * details.
7 */
8
19#ifndef PERIPH_CONF_COMMON_H
20#define PERIPH_CONF_COMMON_H
21
22#include "periph_cpu.h"
23
24#ifdef __cplusplus
25extern "C"
26{
27#endif
28
33static const clock_config_t clock_config = {
34 /*
35 * This configuration results in the system running with the internal clock
36 * with the following clock frequencies:
37 * Core: 48 MHz
38 * Bus: 24 MHz
39 * Flash: 24 MHz
40 */
41 .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(1),
42 /* unsure if this RTC load cap configuration is correct, but it matches the
43 * settings used by the example code in the NXP provided SDK */
44 .rtc_clc = 0,
45 /* Use the 32 kHz oscillator as ERCLK32K. Note that the values here have a
46 * different mapping for the KW41Z than the values used in the Kinetis K series */
47 .osc32ksel = SIM_SOPT1_OSC32KSEL(0),
48 .clock_flags =
49 KINETIS_CLOCK_OSC0_EN | /* Enable RSIM oscillator */
50 KINETIS_CLOCK_RTCOSC_EN |
51 KINETIS_CLOCK_USE_FAST_IRC |
52 KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
53 KINETIS_CLOCK_MCGIRCLK_STOP_EN |
54 0,
55 /* Using FEI mode by default, the external crystal settings below are only
56 * used if mode is changed to an external mode (PEE, FBE, or FEE) */
57 .default_mode = KINETIS_MCG_MODE_FEI,
58 /* The crystal connected to RSIM OSC is 32 MHz */
59 .erc_range = KINETIS_MCG_ERC_RANGE_VERY_HIGH,
60 .osc_clc = 0, /* no load cap configuration */
61 .oscsel = MCG_C7_OSCSEL(0), /* Use RSIM for external clock */
62 .fcrdiv = MCG_SC_FCRDIV(0), /* Fast IRC divide by 1 => 4 MHz */
63 .fll_frdiv = MCG_C1_FRDIV(0b101), /* Divide by 1024 */
64 .fll_factor_fei = KINETIS_MCG_FLL_FACTOR_1464, /* FEI FLL freq = 48 MHz */
65 .fll_factor_fee = KINETIS_MCG_FLL_FACTOR_1280, /* FEE FLL freq = 40 MHz */
66};
67/* Radio xtal frequency, either 32 MHz or 26 MHz */
68#define CLOCK_RADIOXTAL (32000000ul)
69/* CPU core clock, the MCG clock output frequency */
70#define CLOCK_CORECLOCK (48000000ul)
71#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
72#define CLOCK_MCGIRCLK (4000000ul)
79#define PIT_NUMOF (1U)
80#define PIT_CONFIG { \
81 { \
82 .prescaler_ch = 0, \
83 .count_ch = 1, \
84 }, \
85 }
86#define LPTMR_NUMOF (1U)
87#define LPTMR_CONFIG { \
88 { \
89 .dev = LPTMR0, \
90 .irqn = LPTMR0_IRQn, \
91 .src = 2, \
92 .base_freq = 32768u, \
93 } \
94 }
95#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
96#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
97#define LPTMR_ISR_0 isr_lptmr0
104static const uart_conf_t uart_config[] = {
105 {
106 .dev = LPUART0,
107 .freq = CLOCK_MCGIRCLK,
108 .pin_rx = GPIO_PIN(PORT_C, 6),
109 .pin_tx = GPIO_PIN(PORT_C, 7),
110 .pcr_rx = PORT_PCR_MUX(4),
111 .pcr_tx = PORT_PCR_MUX(4),
112 .irqn = LPUART0_IRQn,
113 .scgc_addr = &SIM->SCGC5,
114 .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
115 .mode = UART_MODE_8N1,
116 .type = KINETIS_LPUART,
117 },
118};
119#define UART_NUMOF ARRAY_SIZE(uart_config)
120#define LPUART_0_ISR isr_lpuart0
121/* Use MCGIRCLK (internal reference 4 MHz clock) */
122#define LPUART_0_SRC 3
135static const uint32_t spi_clk_config[] = {
136 (
137 SPI_CTAR_PBR(2) | SPI_CTAR_BR(5) | /* -> 100000Hz */
138 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(4) |
139 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(4) |
140 SPI_CTAR_PDT(2) | SPI_CTAR_DT(4)
141 ),
142 (
143 SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | /* -> 400000Hz */
144 SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(2) |
145 SPI_CTAR_PASC(2) | SPI_CTAR_ASC(2) |
146 SPI_CTAR_PDT(2) | SPI_CTAR_DT(2)
147 ),
148 (
149 SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | /* -> 1000000Hz */
150 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(3) |
151 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(3) |
152 SPI_CTAR_PDT(0) | SPI_CTAR_DT(3)
153 ),
154 (
155 SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
156 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
157 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
158 SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
159 ),
160 (
161 SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 4000000Hz */
162 SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(0) |
163 SPI_CTAR_PASC(0) | SPI_CTAR_ASC(0) |
164 SPI_CTAR_PDT(0) | SPI_CTAR_DT(0)
165 )
166};
173#define KINETIS_TRNG TRNG
176#ifdef __cplusplus
177}
178#endif
179
180#endif /* PERIPH_CONF_COMMON_H */
@ PORT_C
port C
Definition periph_cpu.h:49
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
static const uart_conf_t uart_config[]
Static array with configuration for declared UART devices.
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition periph_cpu.h:539
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition periph_cpu.h:294
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219