Register and command definitions for the MKW2XD Modem. More...
Detailed Description
Register and command definitions for the MKW2XD Modem.
Definition in file kw2xrf_reg.h.
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| #define | MKW2XDRF_REG_READ (uint8_t)(1 << 7) |
| Option to for SPI-IF to read a register. | |
| #define | MKW2XDRF_REG_WRITE (uint8_t)(0) |
| Option to for SPI-IF to write a register. | |
| #define | MKW2XDRF_BUF_READ (uint8_t)(1 << 7 | 1 << 6) |
| Option to for SPI-IF to read data from the RX/TX-Buffer. | |
| #define | MKW2XDRF_BUF_WRITE (uint8_t)(1 << 6) |
| Option to for SPI-IF to write data to RX/TX-Buffer. | |
| #define | MKW2XDRF_BUF_BYTE_READ (uint8_t)(1 << 7 | 1 << 6 | 1 << 5) |
| Option for SPI-IF. | |
| #define | MKW2XDRF_BUF_BYTE_WRITE (uint8_t)(1 << 6 | 1 << 5) |
| Option for SPI-IF. | |
| #define | MKW2XDM_IRQSTS1_RX_FRM_PEND (1 << 7) |
| #define | MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ (1 << 6) |
| #define | MKW2XDM_IRQSTS1_FILTERFAIL_IRQ (1 << 5) |
| #define | MKW2XDM_IRQSTS1_RXWTRMRKIRQ (1 << 4) |
| #define | MKW2XDM_IRQSTS1_CCAIRQ (1 << 3) |
| #define | MKW2XDM_IRQSTS1_RXIRQ (1 << 2) |
| #define | MKW2XDM_IRQSTS1_TXIRQ (1 << 1) |
| #define | MKW2XDM_IRQSTS1_SEQIRQ (1 << 0) |
| #define | MKW2XDM_IRQSTS2_CRCVALID (1 << 7) |
| #define | MKW2XDM_IRQSTS2_CCA (1 << 6) |
| #define | MKW2XDM_IRQSTS2_SRCADDR (1 << 5) |
| #define | MKW2XDM_IRQSTS2_PI (1 << 4) |
| #define | MKW2XDM_IRQSTS2_TMRSTATUS (1 << 3) |
| #define | MKW2XDM_IRQSTS2_PB_ERR_IRQ (1 << 1) |
| #define | MKW2XDM_IRQSTS2_WAKE_IRQ (1 << 0) |
| #define | MKW2XDM_IRQSTS3_TMR4MSK (1 << 7) |
| #define | MKW2XDM_IRQSTS3_TMR3MSK (1 << 6) |
| #define | MKW2XDM_IRQSTS3_TMR2MSK (1 << 5) |
| #define | MKW2XDM_IRQSTS3_TMR1MSK (1 << 4) |
| #define | MKW2XDM_IRQSTS3_TMR4IRQ (1 << 3) |
| #define | MKW2XDM_IRQSTS3_TMR3IRQ (1 << 2) |
| #define | MKW2XDM_IRQSTS3_TMR2IRQ (1 << 1) |
| #define | MKW2XDM_IRQSTS3_TMR1IRQ (1 << 0) |
| #define | MKW2XDM_IRQSTS3_TMR_IRQ_MASK 0xfu |
| #define | MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT 0x0u |
| #define | MKW2XDM_IRQSTS3_TMR_IRQ(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT))&MKW2XDM_IRQSTS3_TMR_IRQ_MASK) |
| #define | MKW2XDM_PHY_CTRL1_TMRTRIGEN (1 << 7) |
| #define | MKW2XDM_PHY_CTRL1_SLOTTED (1 << 6) |
| #define | MKW2XDM_PHY_CTRL1_CCABFRTX (1 << 5) |
| #define | MKW2XDM_PHY_CTRL1_RXACKRQD (1 << 4) |
| #define | MKW2XDM_PHY_CTRL1_AUTOACK (1 << 3) |
| #define | MKW2XDM_PHY_CTRL1_XCVSEQ_MASK 0x07u |
| #define | MKW2XDM_PHY_CTRL1_XCVSEQ(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PHY_CTRL1_XCVSEQ_MASK) |
| #define | MKW2XDM_PHY_CTRL2_CRC_MSK (1 << 7) |
| #define | MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK (1 << 6) |
| #define | MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK (1 << 5) |
| #define | MKW2XDM_PHY_CTRL2_RX_WMRK_MSK (1 << 4) |
| #define | MKW2XDM_PHY_CTRL2_CCAMSK (1 << 3) |
| #define | MKW2XDM_PHY_CTRL2_RXMSK (1 << 2) |
| #define | MKW2XDM_PHY_CTRL2_TXMSK (1 << 1) |
| #define | MKW2XDM_PHY_CTRL2_SEQMSK (1 << 0) |
| #define | MKW2XDM_PHY_CTRL3_TMR4CMP_EN (1 << 7) |
| #define | MKW2XDM_PHY_CTRL3_TMR3CMP_EN (1 << 6) |
| #define | MKW2XDM_PHY_CTRL3_TMR2CMP_EN (1 << 5) |
| #define | MKW2XDM_PHY_CTRL3_TMR1CMP_EN (1 << 4) |
| #define | MKW2XDM_PHY_CTRL3_PB_ERR_MSK (1 << 1) |
| #define | MKW2XDM_PHY_CTRL3_WAKE_MSK (1 << 0) |
| #define | MKW2XDM_RX_FRM_LENGTH_MASK 0x7Fu |
| #define | MKW2XDM_PHY_CTRL4_TRCV_MSK (1 << 7) |
| #define | MKW2XDM_PHY_CTRL4_TC3TMOUT (1 << 6) |
| #define | MKW2XDM_PHY_CTRL4_PANCORDNTR0 (1 << 5) |
| #define | MKW2XDM_PHY_CTRL4_CCATYPE_MASK 0x18u |
| #define | MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT 3 |
| #define | MKW2XDM_PHY_CTRL4_CCATYPE(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT))&MKW2XDM_PHY_CTRL4_CCATYPE_MASK) |
| #define | MKW2XDM_PHY_CTRL4_TMRLOAD (1 << 2) |
| #define | MKW2XDM_PHY_CTRL4_PROMISCUOUS (1 << 1) |
| #define | MKW2XDM_PHY_CTRL4_TC2PRIME_EN (1 << 0) |
| #define | MKW2XDM_SRC_CTRL_INDEX_MASK 0xF0u |
| #define | MKW2XDM_SRC_CTRL_INDEX_SHIFT 4 |
| #define | MKW2XDM_SRC_CTRL_ACK_FRM_PND (1 << 3) |
| #define | MKW2XDM_SRC_CTRL_SRCADDR_EN (1 << 2) |
| #define | MKW2XDM_SRC_CTRL_INDEX_EN (1 << 1) |
| #define | MKW2XDM_SRC_CTRL_INDEX_DISABLE (1 << 0) |
| #define | MKW2XDM_PLL_INT0_MASK 0x1Fu |
| #define | MKW2XDM_PLL_INT0_VAL(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PLL_INT0_MASK) |
| #define | MKW2XDM_PA_PWR_MASK 0x1Fu |
| #define | MKW2XDM_PA_PWR(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PA_PWR_MASK) |
| #define | MKW2XDM_CLK_OUT_EXTEND (1 << 7) |
| #define | MKW2XDM_CLK_OUT_HIZ (1 << 6) |
| #define | MKW2XDM_CLK_OUT_SR (1 << 5) |
| #define | MKW2XDM_CLK_OUT_DS (1 << 4) |
| #define | MKW2XDM_CLK_OUT_EN (1 << 3) |
| #define | MKW2XDM_CLK_OUT_DIV_MASK 0x03u |
| #define | MKW2XDM_CLK_OUT_DIV(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_CLK_OUT_DIV_MASK) |
| #define | MKW2XDM_PWR_MODES_XTAL_READY (1 << 5) |
| #define | MKW2XDM_PWR_MODES_XTALEN (1 << 4) |
| #define | MKW2XDM_PWR_MODES_AUTODOZE (1 << 1) |
| #define | MKW2XDM_PWR_MODES_PMC_MODE (1 << 0) |
| #define | MKW2XDMI_PART_ID_MANUF_ID_MASK 0x60u |
| #define | MKW2XDMI_PART_ID_VERSION_MASK 0x1Cu |
| #define | MKW2XDMI_PART_ID_MASK_SET_MASK 0x07u |
| #define | MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK 0xC0u |
| #define | MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT 6 |
| #define | MKW2XDMI_RX_FRAME_FILTER_FRM_VER(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT))&MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK) |
| #define | MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS (1 << 5) |
| #define | MKW2XDMI_RX_FRAME_FILTER_NS_FT (1 << 4) |
| #define | MKW2XDMI_RX_FRAME_FILTER_CMD_FT (1 << 3) |
| #define | MKW2XDMI_RX_FRAME_FILTER_ACK_FT (1 << 2) |
| #define | MKW2XDMI_RX_FRAME_FILTER_DATA_FT (1 << 1) |
| #define | MKW2XDMI_RX_FRAME_FILTER_BEACON_FT (1 << 0) |
| #define | MKW2XDMI_PLL_INT1_MASK 0x1Fu |
| #define | MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK 0xF0 |
| #define | MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT 4 |
| #define | MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT))&MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK) |
| #define | MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK (1 << 3) |
| #define | MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1 (1 << 2) |
| #define | MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO (1 << 1) |
| #define | MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK (1 << 0) |
| #define | MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1 (1 << 7) |
| #define | MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0 (1 << 6) |
| #define | MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK 0x3Fu |
| #define | MKW2XDMI_CCA_CTRL_AGC_FRZ_EN (1 << 6) |
| #define | MKW2XDMI_CCA_CTRL_CONT_RSSI_EN (1 << 5) |
| #define | MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR (1 << 4) |
| #define | MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR (1 << 3) |
| #define | MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI (1 << 2) |
| #define | MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED (1 << 1) |
| #define | MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1 (1 << 0) |
| #define | MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK 0x70u |
| #define | MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT 4 |
| #define | MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT))&MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK) |
| #define | MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK 0x0Fu |
| #define | MKW2XDMI_TMR_PRESCALE_MASK 0x7u |
| #define | MKW2XDMI_TMR_PRESCALE_SHIFT 0x0u |
| #define | MKW2XDMI_TMR_PRESCALE_SET(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_TMR_PRESCALE_SHIFT))&MKW2XDMI_TMR_PRESCALE_MASK) |
| #define | MKW2XDMI_GPIO_DATA8 (1 << 7) |
| #define | MKW2XDMI_GPIO_DATA7 (1 << 6) |
| #define | MKW2XDMI_GPIO_DATA6 (1 << 5) |
| #define | MKW2XDMI_GPIO_DATA5 (1 << 4) |
| #define | MKW2XDMI_GPIO_DATA4 (1 << 3) |
| #define | MKW2XDMI_GPIO_DATA3 (1 << 2) |
| #define | MKW2XDMI_GPIO_DATA2 (1 << 1) |
| #define | MKW2XDMI_GPIO_DATA1 (1 << 0) |
| #define | MKW2XDMI_GPIO_DIR8 (1 << 7) |
| #define | MKW2XDMI_GPIO_DIR7 (1 << 6) |
| #define | MKW2XDMI_GPIO_DIR6 (1 << 5) |
| #define | MKW2XDMI_GPIO_DIR5 (1 << 4) |
| #define | MKW2XDMI_GPIO_DIR4 (1 << 3) |
| #define | MKW2XDMI_GPIO_DIR3 (1 << 2) |
| #define | MKW2XDMI_GPIO_DIR2 (1 << 1) |
| #define | MKW2XDMI_GPIO_DIR1 (1 << 0) |
| #define | MKW2XDMI_GPIO_PUL_EN8 (1 << 7) |
| #define | MKW2XDMI_GPIO_PUL_EN7 (1 << 6) |
| #define | MKW2XDMI_GPIO_PUL_EN6 (1 << 5) |
| #define | MKW2XDMI_GPIO_PUL_EN5 (1 << 4) |
| #define | MKW2XDMI_GPIO_PUL_EN4 (1 << 3) |
| #define | MKW2XDMI_GPIO_PUL_EN3 (1 << 2) |
| #define | MKW2XDMI_GPIO_PUL_EN2 (1 << 1) |
| #define | MKW2XDMI_GPIO_PUL_EN1 (1 << 0) |
| #define | MKW2XDMI_GPIO_PUL_SEL8 (1 << 7) |
| #define | MKW2XDMI_GPIO_PUL_SEL7 (1 << 6) |
| #define | MKW2XDMI_GPIO_PUL_SEL6 (1 << 5) |
| #define | MKW2XDMI_GPIO_PUL_SEL5 (1 << 4) |
| #define | MKW2XDMI_GPIO_PUL_SEL4 (1 << 3) |
| #define | MKW2XDMI_GPIO_PUL_SEL3 (1 << 2) |
| #define | MKW2XDMI_GPIO_PUL_SEL2 (1 << 1) |
| #define | MKW2XDMI_GPIO_PUL_SEL1 (1 << 0) |
| #define | MKW2XDMI_GPIO_DS8 (1 << 7) |
| #define | MKW2XDMI_GPIO_DS7 (1 << 6) |
| #define | MKW2XDMI_GPIO_DS6 (1 << 5) |
| #define | MKW2XDMI_GPIO_DS5 (1 << 4) |
| #define | MKW2XDMI_GPIO_DS4 (1 << 3) |
| #define | MKW2XDMI_GPIO_DS3 (1 << 2) |
| #define | MKW2XDMI_GPIO_DS2 (1 << 1) |
| #define | MKW2XDMI_GPIO_DS1 (1 << 0) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3 (1 << 7) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_POL2 (1 << 6) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_POL1 (1 << 5) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_POL0 (1 << 4) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_CTRLMODE (1 << 3) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_HZ (1 << 2) |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK 0x03u |
| #define | MKW2XDMI_ANT_PAD_CTRL_ANTX_EN(x) (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK) |
| #define | MKW2XDMI_MISC_PAD_CTRL_MISO_HIZ_EN (1 << 3) |
| #define | MKW2XDMI_MISC_PAD_CTRL_IRQ_B_OD (1 << 2) |
| #define | MKW2XDMI_MISC_PAD_CTRL_NON_GPIO_DS (1 << 1) |
| #define | MKW2XDMI_MISC_PAD_CTRL_ANTX_CURR (1 << 0) |
| #define | MKW2XDMI_ANT_AGC_CTRL_SNF_EN (1 << 7) |
| #define | MKW2XDMI_ANT_AGC_CTRL_AGC_EN (1 << 6) |
| #define | MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK 0x30u |
| #define | MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT 4 |
| #define | MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL(x) (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT))&MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK) |
| #define | MKW2XDMI_ANT_AGC_CTRL_ANTX (1 << 1) |
| #define | MKW2XDMI_ANT_AGC_CTRL_AD_EN (1 << 0) |
| #define | MKW2XDMI_LPPS_CTRL_LPPS_EN (1 << 0) |
| #define | MKW2XDMI_SOFT_RESET_SOG_RST (1 << 7) |
| #define | MKW2XDMI_SOFT_RESET_REGS_RST (1 << 4) |
| #define | MKW2XDMI_SOFT_RESET_PLL_RST (1 << 3) |
| #define | MKW2XDMI_SOFT_RESET_TX_RST (1 << 2) |
| #define | MKW2XDMI_SOFT_RESET_RX_RST (1 << 1) |
| #define | MKW2XDMI_SOFT_RESET_SEQ_MGR_RST (1 << 0) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK 0x3 |
| #define | MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT 6 |
| #define | MKW2XDMI_SEQ_MGR_CTRL_NO_RX_RECYCLE (1 << 5) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_LATCH_PREAMBLE (1 << 4) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1 << 3) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1 << 2) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_PSM_LOCK_DIS (1 << 1) |
| #define | MKW2XDMI_SEQ_MGR_CTRL_PLL_ABORT_OVRD (1 << 0) |
| #define | MKW2XDMI_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1 << 7) |
| #define | MKW2XDMI_SEQ_MGR_STS_RX_MODE (1 << 6) |
| #define | MKW2XDMI_SEQ_MGR_STS_RX_TIMEOUT_PENDING (1 << 5) |
| #define | MKW2XDMI_SEQ_MGR_STS_NEW_SEQ_INHIBIT (1 << 4) |
| #define | MKW2XDMI_SEQ_MGR_STS_SEQ_IDLE (1 << 3) |
| #define | MKW2XDMI_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK 7 |
| #define | MKW2XDMI_ABORT_STS_PLL_ABORTED (1 << 2) |
| #define | MKW2XDMI_ABORT_STS_TC3_ABORTED (1 << 1) |
| #define | MKW2XDMI_ABORT_STS_SW_ABORTED (1 << 0) |
| #define | MKW2XDMI_TESTMODE_CTRL_HOT_ANT (1 << 4) |
| #define | MKW2XDMI_TESTMODE_CTRL_IDEAL_RSSI_EN (1 << 3) |
| #define | MKW2XDMI_TESTMODE_CTRL_IDEAL_PFC_EN (1 << 2) |
| #define | MKW2XDMI_TESTMODE_CTRL_CONTINUOUS_EN (1 << 1) |
| #define | MKW2XDMI_TESTMODE_CTRL_FPGA_EN (1 << 0) |
| #define | MKW2XDMI_DTM_CTRL1_ATM_LOCKED (1 << 7) |
| #define | MKW2XDMI_DTM_CTRL1_DTM_EN (1 << 6) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE5 (1 << 5) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE4 (1 << 4) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE3 (1 << 3) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE2 (1 << 2) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE1 (1 << 1) |
| #define | MKW2XDMI_DTM_CTRL1_PAGE0 (1 << 0) |
| #define | MKW2XDMI_TX_MODE_CTRL_TX_INV (1 << 4) |
| #define | MKW2XDMI_TX_MODE_CTRL_BT_EN (1 << 3) |
| #define | MKW2XDMI_TX_MODE_CTRL_DTS2 (1 << 2) |
| #define | MKW2XDMI_TX_MODE_CTRL_DTS1 (1 << 1) |
| #define | MKW2XDMI_TX_MODE_CTRL_DTS0 (1 << 0) |
| #define | MKW2XDMI_TX_MODE_CTRL_DTS_MASK 7 |
| enum | kw2xrf_physeq_t { XCVSEQ_IDLE = 0 , XCVSEQ_RECEIVE , XCVSEQ_TRANSMIT , XCVSEQ_CCA , XCVSEQ_TX_RX , XCVSEQ_CONTINUOUS_CCA } |
| Transceiver Sequence Selector, define Values for XCVSEQ. More... | |
| enum | mkw2xdrf_dregister { MKW2XDM_IRQSTS1 = 0x0 , MKW2XDM_IRQSTS2 = 0x1 , MKW2XDM_IRQSTS3 = 0x2 , MKW2XDM_PHY_CTRL1 = 0x3 , MKW2XDM_PHY_CTRL2 = 0x4 , MKW2XDM_PHY_CTRL3 = 0x5 , MKW2XDM_RX_FRM_LEN = 0x6 , MKW2XDM_PHY_CTRL4 = 0x7 , MKW2XDM_SRC_CTRL = 0x8 , MKW2XDM_SRC_ADDRS_SUM_LSB = 0x9 , MKW2XDM_SRC_ADDRS_SUM_MSB = 0xa , MKW2XDM_CCA1_ED_FNL = 0xb , MKW2XDM_EVENT_TIMER_LSB = 0xc , MKW2XDM_EVENT_TIMER_MSB = 0xd , MKW2XDM_EVENT_TIMER_USB = 0xe , MKW2XDM_TIMESTAMP_LSB = 0xf , MKW2XDM_TIMESTAMP_MSB = 0x10 , MKW2XDM_TIMESTAMP_USB = 0x11 , MKW2XDM_T3CMP_LSB = 0x12 , MKW2XDM_T3CMP_MSB = 0x13 , MKW2XDM_T3CMP_USB = 0x14 , MKW2XDM_T2PRIMECMP_LSB = 0x15 , MKW2XDM_T2PRIMECMP_MSB = 0x16 , MKW2XDM_T1CMP_LSB = 0x17 , MKW2XDM_T1CMP_MSB = 0x18 , MKW2XDM_T1CMP_USB = 0x19 , MKW2XDM_T2CMP_LSB = 0x1a , MKW2XDM_T2CMP_MSB = 0x1b , MKW2XDM_T2CMP_USB = 0x1c , MKW2XDM_T4CMP_LSB = 0x1d , MKW2XDM_T4CMP_MSB = 0x1e , MKW2XDM_T4CMP_USB = 0x1f , MKW2XDM_PLL_INT0 = 0x20 , MKW2XDM_PLL_FRAC0_LSB = 0x21 , MKW2XDM_PLL_FRAC0_MSB = 0x22 , MKW2XDM_PA_PWR = 0x23 , MKW2XDM_SEQ_STATE = 0x24 , MKW2XDM_LQI_VALUE = 0x25 , MKW2XDM_RSSI_CCA_CNT = 0x26 , MKW2XDM_ASM_CTRL1 = 0x28 , MKW2XDM_ASM_CTRL2 = 0x29 , MKW2XDM_ASM_DATA_0 = 0x2A , MKW2XDM_ASM_DATA_1 = 0x2B , MKW2XDM_ASM_DATA_2 = 0x2C , MKW2XDM_ASM_DATA_3 = 0x2D , MKW2XDM_ASM_DATA_4 = 0x2E , MKW2XDM_ASM_DATA_5 = 0x2F , MKW2XDM_ASM_DATA_6 = 0x30 , MKW2XDM_ASM_DATA_7 = 0x31 , MKW2XDM_ASM_DATA_8 = 0x32 , MKW2XDM_ASM_DATA_9 = 0x33 , MKW2XDM_ASM_DATA_A = 0x34 , MKW2XDM_ASM_DATA_B = 0x35 , MKW2XDM_ASM_DATA_C = 0x36 , MKW2XDM_ASM_DATA_D = 0x37 , MKW2XDM_ASM_DATA_E = 0x38 , MKW2XDM_ASM_DATA_F = 0x39 , MKW2XDM_OVERWRITE_VER = 0x3b , MKW2XDM_CLK_OUT_CTRL = 0x3c , MKW2XDM_PWR_MODES = 0x3d , MKW2XDM_IAR_INDEX = 0x3e , MKW2XDM_IAR_DATA = 0x3f } |
| enum | mkw2xdrf_iregister { MKW2XDMI_PART_ID = 0x00 , MKW2XDMI_XTAL_TRIM = 0x01 , MKW2XDMI_MACPANID0_LSB = 0x03 , MKW2XDMI_MACPANID0_MSB = 0x04 , MKW2XDMI_MACSHORTADDRS0_LSB = 0x05 , MKW2XDMI_MACSHORTADDRS0_MSB = 0x06 , MKW2XDMI_MACLONGADDRS0_0 = 0x07 , MKW2XDMI_MACLONGADDRS0_1 = 0x08 , MKW2XDMI_MACLONGADDRS0_2 = 0x09 , MKW2XDMI_MACLONGADDRS0_3 = 0x0a , MKW2XDMI_MACLONGADDRS0_4 = 0x0b , MKW2XDMI_MACLONGADDRS0_5 = 0x0c , MKW2XDMI_MACLONGADDRS0_6 = 0x0d , MKW2XDMI_MACLONGADDRS0_7 = 0x0e , MKW2XDMI_RX_FRAME_FILTER = 0x0f , MKW2XDMI_PLL_INT1 = 0x10 , MKW2XDMI_PLL_FRAC1_LSB = 0x11 , MKW2XDMI_PLL_FRAC1_MSB = 0x12 , MKW2XDMI_MACPANID1_LSB = 0x13 , MKW2XDMI_MACPANID1_MSB = 0x14 , MKW2XDMI_MACSHORTADDRS1_LSB = 0x15 , MKW2XDMI_MACSHORTADDRS1_MSB = 0x16 , MKW2XDMI_MACLONGADDRS1_0 = 0x17 , MKW2XDMI_MACLONGADDRS1_1 = 0x18 , MKW2XDMI_MACLONGADDRS1_2 = 0x19 , MKW2XDMI_MACLONGADDRS1_3 = 0x1a , MKW2XDMI_MACLONGADDRS1_4 = 0x1b , MKW2XDMI_MACLONGADDRS1_5 = 0x1c , MKW2XDMI_MACLONGADDRS1_6 = 0x1d , MKW2XDMI_MACLONGADDRS1_7 = 0x1e , MKW2XDMI_DUAL_PAN_CTRL = 0x1f , MKW2XDMI_DUAL_PAN_DWELL = 0x20 , MKW2XDMI_DUAL_PAN_STS = 0x21 , MKW2XDMI_CCA1_THRESH = 0x22 , MKW2XDMI_CCA1_ED_OFFSET_COMP = 0x23 , MKW2XDMI_LQI_OFFSET_COMP = 0x24 , MKW2XDMI_CCA_CTRL = 0x25 , MKW2XDMI_CCA2_CORR_PEAKS = 0x26 , MKW2XDMI_CCA2_THRESH = 0x27 , MKW2XDMI_TMR_PRESCALE = 0x28 , MKW2XDMI_GPIO_DATA = 0x2a , MKW2XDMI_GPIO_DIR = 0x2b , MKW2XDMI_GPIO_PUL_EN = 0x2c , MKW2XDMI_GPIO_SEL = 0x2d , MKW2XDMI_GPIO_DS = 0x2e , MKW2XDMI_ANT_PAD_CTRL = 0x30 , MKW2XDMI_MISC_PAD_CTRL = 0x31 , MKW2XDMI_BSM_CTRL = 0x32 , MKW2XDMI__RNG = 0x34 , MKW2XDMI_RX_BYTE_COUNT = 0x35 , MKW2XDMI_RX_WTR_MARK = 0x36 , MKW2XDMI_SOFT_RESET = 0x37 , MKW2XDMI_TXDELAY = 0x38 , MKW2XDMI_ACKDELAY = 0x39 , MKW2XDMI_SEQ_MGR_CTRL = 0x3A , MKW2XDMI_SEQ_MGR_STS = 0x3B , MKW2XDMI_SEQ_T_STS = 0x3C , MKW2XDMI_ABORT_STS = 0x3D , MKW2XDMI_CCCA_BUSY_CNT = 0x3E , MKW2XDMI_SRC_ADDR_CHECKSUM1 = 0x3F , MKW2XDMI_SRC_ADDR_CHECKSUM2 = 0x40 , MKW2XDMI_SRC_TBL_VALID1 = 0x41 , MKW2XDMI_SRC_TBL_VALID2 = 0x42 , MKW2XDMI_FILTERFAIL_CODE1 = 0x43 , MKW2XDMI_FILTERFAIL_CODE2 = 0x44 , MKW2XDMI_SLOT_PRELOAD = 0x45 , MKW2XDMI_CORR_VT = 0x47 , MKW2XDMI_SYNC_CTRL = 0x48 , MKW2XDMI_PN_LSB_0 = 0x49 , MKW2XDMI_PN_LSB_1 = 0x4A , MKW2XDMI_PN_MSB_0 = 0x4B , MKW2XDMI_PN_MSB_1 = 0x4C , MKW2XDMI_CORR_NVAL = 0x4D , MKW2XDMI_TX_MODE_CTRL = 0x4E , MKW2XDMI_SNF_THR = 0x4F , MKW2XDMI_FAD_THR = 0x50 , MKW2XDMI_ANT_AGC_CTRL = 0x51 , MKW2XDMI_AGC_THR1 = 0x52 , MKW2XDMI_AGC_THR2 = 0x53 , MKW2XDMI_AGC_HYS = 0x54 , MKW2XDMI_AFC = 0x55 , MKW2XDMI_LPPS_CTRL = 0x56 , MKW2XDMI_PHY_STS = 0x58 , MKW2XDMI_RX_MAX_CORR = 0x59 , MKW2XDMI_RX_MAX_PREAMBLE = 0x5A , MKW2XDMI_RSSI = 0x5B , MKW2XDMI_PLL_DIG_CTRL = 0x5E , MKW2XDMI_VCO_CAL = 0x5F , MKW2XDMI_VCO_BEST_DIFF = 0x60 , MKW2XDMI_VCO_BIAS = 0x61 , MKW2XDMI_KMOD_CTRL = 0x62 , MKW2XDMI_KMOD_CAL = 0x63 , MKW2XDMI_PA_CAL = 0x64 , MKW2XDMI_PA_PWRCAL = 0x65 , MKW2XDMI_ATT_RSSI1 = 0x66 , MKW2XDMI_ATT_RSSI2 = 0x67 , MKW2XDMI_RSSI_OFFSET = 0x68 , MKW2XDMI_RSSI_SLOPE = 0x69 , MKW2XDMI_RSSI_CAL1 = 0x6A , MKW2XDMI_RSSI_CAL2 = 0x6B , MKW2XDMI_XTAL_CTRL = 0x6E , MKW2XDMI_XTAL_COMP_MIN = 0x6F , MKW2XDMI_XTAL_COMP_MAX = 0x70 , MKW2XDMI_XTAL_GM = 0x71 , MKW2XDMI_LNA_TUNE = 0x74 , MKW2XDMI_LNA_AGCGAIN = 0x75 , MKW2XDMI_CHF_PMA_GAIN = 0x78 , MKW2XDMI_CHF_IBUF = 0x79 , MKW2XDMI_CHF_QBUF = 0x7A , MKW2XDMI_CHF_IRIN = 0x7B , MKW2XDMI_CHF_QRIN = 0x7C , MKW2XDMI_CHF_IL = 0x7D , MKW2XDMI_CHF_QL = 0x7E , MKW2XDMI_CHF_CC1 = 0x7F , MKW2XDMI_CHF_CCL = 0x80 , MKW2XDMI_CHF_CC2 = 0x81 , MKW2XDMI_CHF_IROUT = 0x82 , MKW2XDMI_CHF_QROUT = 0x83 , MKW2XDMI_RSSI_CTRL = 0x86 , MKW2XDMI_PA_BIAS = 0x89 , MKW2XDMI_PA_TUNING = 0x8A , MKW2XDMI_PMC_HP_TRIM = 0x8D , MKW2XDMI_VREGA_TRIM = 0x8E , MKW2XDMI_VCO_CTRL1 = 0x91 , MKW2XDMI_VCO_CTRL2 = 0x92 , MKW2XDMI_ANA_SPARE_OUT1 = 0x95 , MKW2XDMI_ANA_SPARE_OUT2 = 0x96 , MKW2XDMI_ANA_SPARE_IN = 0x97 , MKW2XDMI_MISCELLANEOUS = 0x98 , MKW2XDMI_SEQ_MGR_OVRD0 = 0x9A , MKW2XDMI_SEQ_MGR_OVRD1 = 0x9B , MKW2XDMI_SEQ_MGR_OVRD2 = 0x9C , MKW2XDMI_SEQ_MGR_OVRD3 = 0x9D , MKW2XDMI_SEQ_MGR_OVRD4 = 0x9E , MKW2XDMI_SEQ_MGR_OVRD5 = 0x9F , MKW2XDMI_SEQ_MGR_OVRD6 = 0xA0 , MKW2XDMI_SEQ_MGR_OVRD7 = 0xA1 , MKW2XDMI_TESTMODE_CTRL = 0xA3 , MKW2XDMI_DTM_CTRL1 = 0xA4 , MKW2XDMI_DTM_CTRL2 = 0xA5 , MKW2XDMI_ATM_CTRL1 = 0xA6 , MKW2XDMI_ATM_CTRL2 = 0xA7 , MKW2XDMI_ATM_CTRL3 = 0xA8 , MKW2XDMI_LIM_FE_TEST_CTRL = 0xAA , MKW2XDMI_CHF_TEST_CTRL = 0xAB , MKW2XDMI_VCO_TEST_CTRL = 0xAC , MKW2XDMI_PLL_TEST_CTRL = 0xAD , MKW2XDMI_PA_TEST_CTRL = 0xAE , MKW2XDMI_PMC_TEST_CTRL = 0xAF , MKW2XDMI_SCAN_DTM_PROTECT_1 = 0xFE , MKW2XDMI_SCAN_DTM_PROTECT_0 = 0xFF } |
Macro Definition Documentation
◆ MKW2XDM_CLK_OUT_DIV
| #define MKW2XDM_CLK_OUT_DIV | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_CLK_OUT_DIV_MASK) |
Definition at line 238 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_DIV_MASK
| #define MKW2XDM_CLK_OUT_DIV_MASK 0x03u |
Definition at line 237 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_DS
| #define MKW2XDM_CLK_OUT_DS (1 << 4) |
Definition at line 235 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_EN
| #define MKW2XDM_CLK_OUT_EN (1 << 3) |
Definition at line 236 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_EXTEND
| #define MKW2XDM_CLK_OUT_EXTEND (1 << 7) |
Definition at line 232 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_HIZ
| #define MKW2XDM_CLK_OUT_HIZ (1 << 6) |
Definition at line 233 of file kw2xrf_reg.h.
◆ MKW2XDM_CLK_OUT_SR
| #define MKW2XDM_CLK_OUT_SR (1 << 5) |
Definition at line 234 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_CCAIRQ
| #define MKW2XDM_IRQSTS1_CCAIRQ (1 << 3) |
Definition at line 158 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_FILTERFAIL_IRQ
| #define MKW2XDM_IRQSTS1_FILTERFAIL_IRQ (1 << 5) |
Definition at line 156 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ
| #define MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ (1 << 6) |
Definition at line 155 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_RX_FRM_PEND
| #define MKW2XDM_IRQSTS1_RX_FRM_PEND (1 << 7) |
Definition at line 154 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_RXIRQ
| #define MKW2XDM_IRQSTS1_RXIRQ (1 << 2) |
Definition at line 159 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_RXWTRMRKIRQ
| #define MKW2XDM_IRQSTS1_RXWTRMRKIRQ (1 << 4) |
Definition at line 157 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_SEQIRQ
| #define MKW2XDM_IRQSTS1_SEQIRQ (1 << 0) |
Definition at line 161 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS1_TXIRQ
| #define MKW2XDM_IRQSTS1_TXIRQ (1 << 1) |
Definition at line 160 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_CCA
| #define MKW2XDM_IRQSTS2_CCA (1 << 6) |
Definition at line 164 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_CRCVALID
| #define MKW2XDM_IRQSTS2_CRCVALID (1 << 7) |
Definition at line 163 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_PB_ERR_IRQ
| #define MKW2XDM_IRQSTS2_PB_ERR_IRQ (1 << 1) |
Definition at line 168 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_PI
| #define MKW2XDM_IRQSTS2_PI (1 << 4) |
Definition at line 166 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_SRCADDR
| #define MKW2XDM_IRQSTS2_SRCADDR (1 << 5) |
Definition at line 165 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_TMRSTATUS
| #define MKW2XDM_IRQSTS2_TMRSTATUS (1 << 3) |
Definition at line 167 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS2_WAKE_IRQ
| #define MKW2XDM_IRQSTS2_WAKE_IRQ (1 << 0) |
Definition at line 169 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR1IRQ
| #define MKW2XDM_IRQSTS3_TMR1IRQ (1 << 0) |
Definition at line 178 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR1MSK
| #define MKW2XDM_IRQSTS3_TMR1MSK (1 << 4) |
Definition at line 174 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR2IRQ
| #define MKW2XDM_IRQSTS3_TMR2IRQ (1 << 1) |
Definition at line 177 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR2MSK
| #define MKW2XDM_IRQSTS3_TMR2MSK (1 << 5) |
Definition at line 173 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR3IRQ
| #define MKW2XDM_IRQSTS3_TMR3IRQ (1 << 2) |
Definition at line 176 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR3MSK
| #define MKW2XDM_IRQSTS3_TMR3MSK (1 << 6) |
Definition at line 172 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR4IRQ
| #define MKW2XDM_IRQSTS3_TMR4IRQ (1 << 3) |
Definition at line 175 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR4MSK
| #define MKW2XDM_IRQSTS3_TMR4MSK (1 << 7) |
Definition at line 171 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR_IRQ
| #define MKW2XDM_IRQSTS3_TMR_IRQ | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT))&MKW2XDM_IRQSTS3_TMR_IRQ_MASK) |
Definition at line 181 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR_IRQ_MASK
| #define MKW2XDM_IRQSTS3_TMR_IRQ_MASK 0xfu |
Definition at line 179 of file kw2xrf_reg.h.
◆ MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT
| #define MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT 0x0u |
Definition at line 180 of file kw2xrf_reg.h.
◆ MKW2XDM_PA_PWR
| #define MKW2XDM_PA_PWR | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PA_PWR_MASK) |
Definition at line 230 of file kw2xrf_reg.h.
◆ MKW2XDM_PA_PWR_MASK
| #define MKW2XDM_PA_PWR_MASK 0x1Fu |
Definition at line 229 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_AUTOACK
| #define MKW2XDM_PHY_CTRL1_AUTOACK (1 << 3) |
Definition at line 187 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_CCABFRTX
| #define MKW2XDM_PHY_CTRL1_CCABFRTX (1 << 5) |
Definition at line 185 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_RXACKRQD
| #define MKW2XDM_PHY_CTRL1_RXACKRQD (1 << 4) |
Definition at line 186 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_SLOTTED
| #define MKW2XDM_PHY_CTRL1_SLOTTED (1 << 6) |
Definition at line 184 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_TMRTRIGEN
| #define MKW2XDM_PHY_CTRL1_TMRTRIGEN (1 << 7) |
Definition at line 183 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_XCVSEQ
| #define MKW2XDM_PHY_CTRL1_XCVSEQ | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PHY_CTRL1_XCVSEQ_MASK) |
Definition at line 189 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL1_XCVSEQ_MASK
| #define MKW2XDM_PHY_CTRL1_XCVSEQ_MASK 0x07u |
Definition at line 188 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_CCAMSK
| #define MKW2XDM_PHY_CTRL2_CCAMSK (1 << 3) |
Definition at line 195 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_CRC_MSK
| #define MKW2XDM_PHY_CTRL2_CRC_MSK (1 << 7) |
Definition at line 191 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK
| #define MKW2XDM_PHY_CTRL2_FILTERFAIL_MSK (1 << 5) |
Definition at line 193 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK
| #define MKW2XDM_PHY_CTRL2_PLL_UNLOCK_MSK (1 << 6) |
Definition at line 192 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_RX_WMRK_MSK
| #define MKW2XDM_PHY_CTRL2_RX_WMRK_MSK (1 << 4) |
Definition at line 194 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_RXMSK
| #define MKW2XDM_PHY_CTRL2_RXMSK (1 << 2) |
Definition at line 196 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_SEQMSK
| #define MKW2XDM_PHY_CTRL2_SEQMSK (1 << 0) |
Definition at line 198 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL2_TXMSK
| #define MKW2XDM_PHY_CTRL2_TXMSK (1 << 1) |
Definition at line 197 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_PB_ERR_MSK
| #define MKW2XDM_PHY_CTRL3_PB_ERR_MSK (1 << 1) |
Definition at line 204 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_TMR1CMP_EN
| #define MKW2XDM_PHY_CTRL3_TMR1CMP_EN (1 << 4) |
Definition at line 203 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_TMR2CMP_EN
| #define MKW2XDM_PHY_CTRL3_TMR2CMP_EN (1 << 5) |
Definition at line 202 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_TMR3CMP_EN
| #define MKW2XDM_PHY_CTRL3_TMR3CMP_EN (1 << 6) |
Definition at line 201 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_TMR4CMP_EN
| #define MKW2XDM_PHY_CTRL3_TMR4CMP_EN (1 << 7) |
Definition at line 200 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL3_WAKE_MSK
| #define MKW2XDM_PHY_CTRL3_WAKE_MSK (1 << 0) |
Definition at line 205 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_CCATYPE
| #define MKW2XDM_PHY_CTRL4_CCATYPE | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT))&MKW2XDM_PHY_CTRL4_CCATYPE_MASK) |
Definition at line 214 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_CCATYPE_MASK
| #define MKW2XDM_PHY_CTRL4_CCATYPE_MASK 0x18u |
Definition at line 212 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT
| #define MKW2XDM_PHY_CTRL4_CCATYPE_SHIFT 3 |
Definition at line 213 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_PANCORDNTR0
| #define MKW2XDM_PHY_CTRL4_PANCORDNTR0 (1 << 5) |
Definition at line 211 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_PROMISCUOUS
| #define MKW2XDM_PHY_CTRL4_PROMISCUOUS (1 << 1) |
Definition at line 216 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_TC2PRIME_EN
| #define MKW2XDM_PHY_CTRL4_TC2PRIME_EN (1 << 0) |
Definition at line 217 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_TC3TMOUT
| #define MKW2XDM_PHY_CTRL4_TC3TMOUT (1 << 6) |
Definition at line 210 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_TMRLOAD
| #define MKW2XDM_PHY_CTRL4_TMRLOAD (1 << 2) |
Definition at line 215 of file kw2xrf_reg.h.
◆ MKW2XDM_PHY_CTRL4_TRCV_MSK
| #define MKW2XDM_PHY_CTRL4_TRCV_MSK (1 << 7) |
Definition at line 209 of file kw2xrf_reg.h.
◆ MKW2XDM_PLL_INT0_MASK
| #define MKW2XDM_PLL_INT0_MASK 0x1Fu |
Definition at line 226 of file kw2xrf_reg.h.
◆ MKW2XDM_PLL_INT0_VAL
| #define MKW2XDM_PLL_INT0_VAL | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDM_PLL_INT0_MASK) |
Definition at line 227 of file kw2xrf_reg.h.
◆ MKW2XDM_PWR_MODES_AUTODOZE
| #define MKW2XDM_PWR_MODES_AUTODOZE (1 << 1) |
Definition at line 242 of file kw2xrf_reg.h.
◆ MKW2XDM_PWR_MODES_PMC_MODE
| #define MKW2XDM_PWR_MODES_PMC_MODE (1 << 0) |
Definition at line 243 of file kw2xrf_reg.h.
◆ MKW2XDM_PWR_MODES_XTAL_READY
| #define MKW2XDM_PWR_MODES_XTAL_READY (1 << 5) |
Definition at line 240 of file kw2xrf_reg.h.
◆ MKW2XDM_PWR_MODES_XTALEN
| #define MKW2XDM_PWR_MODES_XTALEN (1 << 4) |
Definition at line 241 of file kw2xrf_reg.h.
◆ MKW2XDM_RX_FRM_LENGTH_MASK
| #define MKW2XDM_RX_FRM_LENGTH_MASK 0x7Fu |
Definition at line 207 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_ACK_FRM_PND
| #define MKW2XDM_SRC_CTRL_ACK_FRM_PND (1 << 3) |
Definition at line 221 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_INDEX_DISABLE
| #define MKW2XDM_SRC_CTRL_INDEX_DISABLE (1 << 0) |
Definition at line 224 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_INDEX_EN
| #define MKW2XDM_SRC_CTRL_INDEX_EN (1 << 1) |
Definition at line 223 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_INDEX_MASK
| #define MKW2XDM_SRC_CTRL_INDEX_MASK 0xF0u |
Definition at line 219 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_INDEX_SHIFT
| #define MKW2XDM_SRC_CTRL_INDEX_SHIFT 4 |
Definition at line 220 of file kw2xrf_reg.h.
◆ MKW2XDM_SRC_CTRL_SRCADDR_EN
| #define MKW2XDM_SRC_CTRL_SRCADDR_EN (1 << 2) |
Definition at line 222 of file kw2xrf_reg.h.
◆ MKW2XDMI_ABORT_STS_PLL_ABORTED
| #define MKW2XDMI_ABORT_STS_PLL_ABORTED (1 << 2) |
Definition at line 536 of file kw2xrf_reg.h.
◆ MKW2XDMI_ABORT_STS_SW_ABORTED
| #define MKW2XDMI_ABORT_STS_SW_ABORTED (1 << 0) |
Definition at line 538 of file kw2xrf_reg.h.
◆ MKW2XDMI_ABORT_STS_TC3_ABORTED
| #define MKW2XDMI_ABORT_STS_TC3_ABORTED (1 << 1) |
Definition at line 537 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_AD_EN
| #define MKW2XDMI_ANT_AGC_CTRL_AD_EN (1 << 0) |
Definition at line 509 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_AGC_EN
| #define MKW2XDMI_ANT_AGC_CTRL_AGC_EN (1 << 6) |
Definition at line 504 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL
| #define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT))&MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK) |
Definition at line 507 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK
| #define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_MASK 0x30u |
Definition at line 505 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT
| #define MKW2XDMI_ANT_AGC_CTRL_AGC_LEVEL_SHIFT 4 |
Definition at line 506 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_ANTX
| #define MKW2XDMI_ANT_AGC_CTRL_ANTX (1 << 1) |
Definition at line 508 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_AGC_CTRL_SNF_EN
| #define MKW2XDMI_ANT_AGC_CTRL_SNF_EN (1 << 7) |
Definition at line 503 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_CTRLMODE
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_CTRLMODE (1 << 3) |
Definition at line 493 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_EN
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<0))&MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK) |
Definition at line 496 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_EN_MASK 0x03u |
Definition at line 495 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_HZ
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_HZ (1 << 2) |
Definition at line 494 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_POL0
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL0 (1 << 4) |
Definition at line 492 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_POL1
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL1 (1 << 5) |
Definition at line 491 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_POL2
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL2 (1 << 6) |
Definition at line 490 of file kw2xrf_reg.h.
◆ MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3
| #define MKW2XDMI_ANT_PAD_CTRL_ANTX_POL3 (1 << 7) |
Definition at line 489 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH
| #define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT))&MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK) |
Definition at line 437 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK
| #define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK 0x70u |
Definition at line 435 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT
| #define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT 4 |
Definition at line 436 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK
| #define MKW2XDMI_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK 0x0Fu |
Definition at line 438 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_AGC_FRZ_EN
| #define MKW2XDMI_CCA_CTRL_AGC_FRZ_EN (1 << 6) |
Definition at line 427 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR
| #define MKW2XDMI_CCA_CTRL_CCA3_AND_NOT_OR (1 << 3) |
Definition at line 430 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_CONT_RSSI_EN
| #define MKW2XDMI_CCA_CTRL_CONT_RSSI_EN (1 << 5) |
Definition at line 428 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1
| #define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_CCA1 (1 << 0) |
Definition at line 433 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED
| #define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_ED (1 << 1) |
Definition at line 432 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI
| #define MKW2XDMI_CCA_CTRL_OWER_COMP_EN_LQI (1 << 2) |
Definition at line 431 of file kw2xrf_reg.h.
◆ MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR
| #define MKW2XDMI_CCA_CTRL_QI_RSSI_NOT_CORR (1 << 4) |
Definition at line 429 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_ATM_LOCKED
| #define MKW2XDMI_DTM_CTRL1_ATM_LOCKED (1 << 7) |
Definition at line 546 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_DTM_EN
| #define MKW2XDMI_DTM_CTRL1_DTM_EN (1 << 6) |
Definition at line 547 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE0
| #define MKW2XDMI_DTM_CTRL1_PAGE0 (1 << 0) |
Definition at line 553 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE1
| #define MKW2XDMI_DTM_CTRL1_PAGE1 (1 << 1) |
Definition at line 552 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE2
| #define MKW2XDMI_DTM_CTRL1_PAGE2 (1 << 2) |
Definition at line 551 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE3
| #define MKW2XDMI_DTM_CTRL1_PAGE3 (1 << 3) |
Definition at line 550 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE4
| #define MKW2XDMI_DTM_CTRL1_PAGE4 (1 << 4) |
Definition at line 549 of file kw2xrf_reg.h.
◆ MKW2XDMI_DTM_CTRL1_PAGE5
| #define MKW2XDMI_DTM_CTRL1_PAGE5 (1 << 5) |
Definition at line 548 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK
| #define MKW2XDMI_DUAL_PAN_CTRL_ACTIVE_NETWORK (1 << 0) |
Definition at line 421 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK
| #define MKW2XDMI_DUAL_PAN_CTRL_CURRENT_NETWORK (1 << 3) |
Definition at line 418 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO
| #define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_AUTO (1 << 1) |
Definition at line 420 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL
| #define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT))&MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK) |
Definition at line 417 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK
| #define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK 0xF0 |
Definition at line 415 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT
| #define MKW2XDMI_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT 4 |
Definition at line 416 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1
| #define MKW2XDMI_DUAL_PAN_CTRL_PANCORDNTR1 (1 << 2) |
Definition at line 419 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK
| #define MKW2XDMI_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK 0x3Fu |
Definition at line 425 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0
| #define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN0 (1 << 6) |
Definition at line 424 of file kw2xrf_reg.h.
◆ MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1
| #define MKW2XDMI_DUAL_PAN_STS_RECD_ON_PAN1 (1 << 7) |
Definition at line 423 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA1
| #define MKW2XDMI_GPIO_DATA1 (1 << 0) |
Definition at line 451 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA2
| #define MKW2XDMI_GPIO_DATA2 (1 << 1) |
Definition at line 450 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA3
| #define MKW2XDMI_GPIO_DATA3 (1 << 2) |
Definition at line 449 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA4
| #define MKW2XDMI_GPIO_DATA4 (1 << 3) |
Definition at line 448 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA5
| #define MKW2XDMI_GPIO_DATA5 (1 << 4) |
Definition at line 447 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA6
| #define MKW2XDMI_GPIO_DATA6 (1 << 5) |
Definition at line 446 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA7
| #define MKW2XDMI_GPIO_DATA7 (1 << 6) |
Definition at line 445 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DATA8
| #define MKW2XDMI_GPIO_DATA8 (1 << 7) |
Definition at line 444 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR1
| #define MKW2XDMI_GPIO_DIR1 (1 << 0) |
Definition at line 460 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR2
| #define MKW2XDMI_GPIO_DIR2 (1 << 1) |
Definition at line 459 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR3
| #define MKW2XDMI_GPIO_DIR3 (1 << 2) |
Definition at line 458 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR4
| #define MKW2XDMI_GPIO_DIR4 (1 << 3) |
Definition at line 457 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR5
| #define MKW2XDMI_GPIO_DIR5 (1 << 4) |
Definition at line 456 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR6
| #define MKW2XDMI_GPIO_DIR6 (1 << 5) |
Definition at line 455 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR7
| #define MKW2XDMI_GPIO_DIR7 (1 << 6) |
Definition at line 454 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DIR8
| #define MKW2XDMI_GPIO_DIR8 (1 << 7) |
Definition at line 453 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS1
| #define MKW2XDMI_GPIO_DS1 (1 << 0) |
Definition at line 487 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS2
| #define MKW2XDMI_GPIO_DS2 (1 << 1) |
Definition at line 486 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS3
| #define MKW2XDMI_GPIO_DS3 (1 << 2) |
Definition at line 485 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS4
| #define MKW2XDMI_GPIO_DS4 (1 << 3) |
Definition at line 484 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS5
| #define MKW2XDMI_GPIO_DS5 (1 << 4) |
Definition at line 483 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS6
| #define MKW2XDMI_GPIO_DS6 (1 << 5) |
Definition at line 482 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS7
| #define MKW2XDMI_GPIO_DS7 (1 << 6) |
Definition at line 481 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_DS8
| #define MKW2XDMI_GPIO_DS8 (1 << 7) |
Definition at line 480 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN1
| #define MKW2XDMI_GPIO_PUL_EN1 (1 << 0) |
Definition at line 469 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN2
| #define MKW2XDMI_GPIO_PUL_EN2 (1 << 1) |
Definition at line 468 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN3
| #define MKW2XDMI_GPIO_PUL_EN3 (1 << 2) |
Definition at line 467 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN4
| #define MKW2XDMI_GPIO_PUL_EN4 (1 << 3) |
Definition at line 466 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN5
| #define MKW2XDMI_GPIO_PUL_EN5 (1 << 4) |
Definition at line 465 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN6
| #define MKW2XDMI_GPIO_PUL_EN6 (1 << 5) |
Definition at line 464 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN7
| #define MKW2XDMI_GPIO_PUL_EN7 (1 << 6) |
Definition at line 463 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_EN8
| #define MKW2XDMI_GPIO_PUL_EN8 (1 << 7) |
Definition at line 462 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL1
| #define MKW2XDMI_GPIO_PUL_SEL1 (1 << 0) |
Definition at line 478 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL2
| #define MKW2XDMI_GPIO_PUL_SEL2 (1 << 1) |
Definition at line 477 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL3
| #define MKW2XDMI_GPIO_PUL_SEL3 (1 << 2) |
Definition at line 476 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL4
| #define MKW2XDMI_GPIO_PUL_SEL4 (1 << 3) |
Definition at line 475 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL5
| #define MKW2XDMI_GPIO_PUL_SEL5 (1 << 4) |
Definition at line 474 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL6
| #define MKW2XDMI_GPIO_PUL_SEL6 (1 << 5) |
Definition at line 473 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL7
| #define MKW2XDMI_GPIO_PUL_SEL7 (1 << 6) |
Definition at line 472 of file kw2xrf_reg.h.
◆ MKW2XDMI_GPIO_PUL_SEL8
| #define MKW2XDMI_GPIO_PUL_SEL8 (1 << 7) |
Definition at line 471 of file kw2xrf_reg.h.
◆ MKW2XDMI_LPPS_CTRL_LPPS_EN
| #define MKW2XDMI_LPPS_CTRL_LPPS_EN (1 << 0) |
Definition at line 511 of file kw2xrf_reg.h.
◆ MKW2XDMI_MISC_PAD_CTRL_ANTX_CURR
| #define MKW2XDMI_MISC_PAD_CTRL_ANTX_CURR (1 << 0) |
Definition at line 501 of file kw2xrf_reg.h.
◆ MKW2XDMI_MISC_PAD_CTRL_IRQ_B_OD
| #define MKW2XDMI_MISC_PAD_CTRL_IRQ_B_OD (1 << 2) |
Definition at line 499 of file kw2xrf_reg.h.
◆ MKW2XDMI_MISC_PAD_CTRL_MISO_HIZ_EN
| #define MKW2XDMI_MISC_PAD_CTRL_MISO_HIZ_EN (1 << 3) |
Definition at line 498 of file kw2xrf_reg.h.
◆ MKW2XDMI_MISC_PAD_CTRL_NON_GPIO_DS
| #define MKW2XDMI_MISC_PAD_CTRL_NON_GPIO_DS (1 << 1) |
Definition at line 500 of file kw2xrf_reg.h.
◆ MKW2XDMI_PART_ID_MANUF_ID_MASK
| #define MKW2XDMI_PART_ID_MANUF_ID_MASK 0x60u |
Definition at line 399 of file kw2xrf_reg.h.
◆ MKW2XDMI_PART_ID_MASK_SET_MASK
| #define MKW2XDMI_PART_ID_MASK_SET_MASK 0x07u |
Definition at line 401 of file kw2xrf_reg.h.
◆ MKW2XDMI_PART_ID_VERSION_MASK
| #define MKW2XDMI_PART_ID_VERSION_MASK 0x1Cu |
Definition at line 400 of file kw2xrf_reg.h.
◆ MKW2XDMI_PLL_INT1_MASK
| #define MKW2XDMI_PLL_INT1_MASK 0x1Fu |
Definition at line 413 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_ACK_FT
| #define MKW2XDMI_RX_FRAME_FILTER_ACK_FT (1 << 2) |
Definition at line 409 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS
| #define MKW2XDMI_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS (1 << 5) |
Definition at line 406 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_BEACON_FT
| #define MKW2XDMI_RX_FRAME_FILTER_BEACON_FT (1 << 0) |
Definition at line 411 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_CMD_FT
| #define MKW2XDMI_RX_FRAME_FILTER_CMD_FT (1 << 3) |
Definition at line 408 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_DATA_FT
| #define MKW2XDMI_RX_FRAME_FILTER_DATA_FT (1 << 1) |
Definition at line 410 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_FRM_VER
| #define MKW2XDMI_RX_FRAME_FILTER_FRM_VER | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT))&MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK) |
Definition at line 405 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK
| #define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_MASK 0xC0u |
Definition at line 403 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT
| #define MKW2XDMI_RX_FRAME_FILTER_FRM_VER_SHIFT 6 |
Definition at line 404 of file kw2xrf_reg.h.
◆ MKW2XDMI_RX_FRAME_FILTER_NS_FT
| #define MKW2XDMI_RX_FRAME_FILTER_NS_FT (1 << 4) |
Definition at line 407 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT
| #define MKW2XDMI_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1 << 2) |
Definition at line 525 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH
| #define MKW2XDMI_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1 << 3) |
Definition at line 524 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_LATCH_PREAMBLE
| #define MKW2XDMI_SEQ_MGR_CTRL_LATCH_PREAMBLE (1 << 4) |
Definition at line 523 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_NO_RX_RECYCLE
| #define MKW2XDMI_SEQ_MGR_CTRL_NO_RX_RECYCLE (1 << 5) |
Definition at line 522 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_PLL_ABORT_OVRD
| #define MKW2XDMI_SEQ_MGR_CTRL_PLL_ABORT_OVRD (1 << 0) |
Definition at line 527 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_PSM_LOCK_DIS
| #define MKW2XDMI_SEQ_MGR_CTRL_PSM_LOCK_DIS (1 << 1) |
Definition at line 526 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK
| #define MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK 0x3 |
Definition at line 520 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT
| #define MKW2XDMI_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT 6 |
Definition at line 521 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_NEW_SEQ_INHIBIT
| #define MKW2XDMI_SEQ_MGR_STS_NEW_SEQ_INHIBIT (1 << 4) |
Definition at line 532 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_RX_MODE
| #define MKW2XDMI_SEQ_MGR_STS_RX_MODE (1 << 6) |
Definition at line 530 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_RX_TIMEOUT_PENDING
| #define MKW2XDMI_SEQ_MGR_STS_RX_TIMEOUT_PENDING (1 << 5) |
Definition at line 531 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_SEQ_IDLE
| #define MKW2XDMI_SEQ_MGR_STS_SEQ_IDLE (1 << 3) |
Definition at line 533 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED
| #define MKW2XDMI_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1 << 7) |
Definition at line 529 of file kw2xrf_reg.h.
◆ MKW2XDMI_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK
| #define MKW2XDMI_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK 7 |
Definition at line 534 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_PLL_RST
| #define MKW2XDMI_SOFT_RESET_PLL_RST (1 << 3) |
Definition at line 515 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_REGS_RST
| #define MKW2XDMI_SOFT_RESET_REGS_RST (1 << 4) |
Definition at line 514 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_RX_RST
| #define MKW2XDMI_SOFT_RESET_RX_RST (1 << 1) |
Definition at line 517 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_SEQ_MGR_RST
| #define MKW2XDMI_SOFT_RESET_SEQ_MGR_RST (1 << 0) |
Definition at line 518 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_SOG_RST
| #define MKW2XDMI_SOFT_RESET_SOG_RST (1 << 7) |
Definition at line 513 of file kw2xrf_reg.h.
◆ MKW2XDMI_SOFT_RESET_TX_RST
| #define MKW2XDMI_SOFT_RESET_TX_RST (1 << 2) |
Definition at line 516 of file kw2xrf_reg.h.
◆ MKW2XDMI_TESTMODE_CTRL_CONTINUOUS_EN
| #define MKW2XDMI_TESTMODE_CTRL_CONTINUOUS_EN (1 << 1) |
Definition at line 543 of file kw2xrf_reg.h.
◆ MKW2XDMI_TESTMODE_CTRL_FPGA_EN
| #define MKW2XDMI_TESTMODE_CTRL_FPGA_EN (1 << 0) |
Definition at line 544 of file kw2xrf_reg.h.
◆ MKW2XDMI_TESTMODE_CTRL_HOT_ANT
| #define MKW2XDMI_TESTMODE_CTRL_HOT_ANT (1 << 4) |
Definition at line 540 of file kw2xrf_reg.h.
◆ MKW2XDMI_TESTMODE_CTRL_IDEAL_PFC_EN
| #define MKW2XDMI_TESTMODE_CTRL_IDEAL_PFC_EN (1 << 2) |
Definition at line 542 of file kw2xrf_reg.h.
◆ MKW2XDMI_TESTMODE_CTRL_IDEAL_RSSI_EN
| #define MKW2XDMI_TESTMODE_CTRL_IDEAL_RSSI_EN (1 << 3) |
Definition at line 541 of file kw2xrf_reg.h.
◆ MKW2XDMI_TMR_PRESCALE_MASK
| #define MKW2XDMI_TMR_PRESCALE_MASK 0x7u |
Definition at line 440 of file kw2xrf_reg.h.
◆ MKW2XDMI_TMR_PRESCALE_SET
| #define MKW2XDMI_TMR_PRESCALE_SET | ( | x | ) | (((uint8_t)(((uint8_t)(x))<<MKW2XDMI_TMR_PRESCALE_SHIFT))&MKW2XDMI_TMR_PRESCALE_MASK) |
Definition at line 442 of file kw2xrf_reg.h.
◆ MKW2XDMI_TMR_PRESCALE_SHIFT
| #define MKW2XDMI_TMR_PRESCALE_SHIFT 0x0u |
Definition at line 441 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_BT_EN
| #define MKW2XDMI_TX_MODE_CTRL_BT_EN (1 << 3) |
Definition at line 556 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_DTS0
| #define MKW2XDMI_TX_MODE_CTRL_DTS0 (1 << 0) |
Definition at line 559 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_DTS1
| #define MKW2XDMI_TX_MODE_CTRL_DTS1 (1 << 1) |
Definition at line 558 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_DTS2
| #define MKW2XDMI_TX_MODE_CTRL_DTS2 (1 << 2) |
Definition at line 557 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_DTS_MASK
| #define MKW2XDMI_TX_MODE_CTRL_DTS_MASK 7 |
Definition at line 560 of file kw2xrf_reg.h.
◆ MKW2XDMI_TX_MODE_CTRL_TX_INV
| #define MKW2XDMI_TX_MODE_CTRL_TX_INV (1 << 4) |
Definition at line 555 of file kw2xrf_reg.h.
◆ MKW2XDRF_BUF_BYTE_READ
| #define MKW2XDRF_BUF_BYTE_READ (uint8_t)(1 << 7 | 1 << 6 | 1 << 5) |
Option for SPI-IF.
Definition at line 73 of file kw2xrf_reg.h.
◆ MKW2XDRF_BUF_BYTE_WRITE
| #define MKW2XDRF_BUF_BYTE_WRITE (uint8_t)(1 << 6 | 1 << 5) |
Option for SPI-IF.
Definition at line 76 of file kw2xrf_reg.h.
◆ MKW2XDRF_BUF_READ
| #define MKW2XDRF_BUF_READ (uint8_t)(1 << 7 | 1 << 6) |
Option to for SPI-IF to read data from the RX/TX-Buffer.
Definition at line 67 of file kw2xrf_reg.h.
◆ MKW2XDRF_BUF_WRITE
| #define MKW2XDRF_BUF_WRITE (uint8_t)(1 << 6) |
Option to for SPI-IF to write data to RX/TX-Buffer.
Definition at line 70 of file kw2xrf_reg.h.
◆ MKW2XDRF_REG_READ
| #define MKW2XDRF_REG_READ (uint8_t)(1 << 7) |
Option to for SPI-IF to read a register.
Definition at line 61 of file kw2xrf_reg.h.
◆ MKW2XDRF_REG_WRITE
| #define MKW2XDRF_REG_WRITE (uint8_t)(0) |
Option to for SPI-IF to write a register.
Definition at line 64 of file kw2xrf_reg.h.
Enumeration Type Documentation
◆ kw2xrf_physeq_t
| enum kw2xrf_physeq_t |
Transceiver Sequence Selector, define Values for XCVSEQ.
Definition at line 79 of file kw2xrf_reg.h.
◆ mkw2xdrf_dregister
| enum mkw2xdrf_dregister |
| Enumerator | |
|---|---|
| MKW2XDM_IRQSTS1 | Interrupt Request Status 1. |
| MKW2XDM_IRQSTS2 | Interrupt Request Status 2. |
| MKW2XDM_IRQSTS3 | Interrupt Request Status 3. |
| MKW2XDM_PHY_CTRL1 | PHY Control 1. |
| MKW2XDM_PHY_CTRL2 | PHY Control 2. |
| MKW2XDM_PHY_CTRL3 | PHY Control 3. |
| MKW2XDM_RX_FRM_LEN | Receive Frame Length. |
| MKW2XDM_PHY_CTRL4 | PHY Control 4. |
| MKW2XDM_SRC_CTRL | SRC Control. |
| MKW2XDM_SRC_ADDRS_SUM_LSB | SRC Address SUM LSB. |
| MKW2XDM_SRC_ADDRS_SUM_MSB | SRC Address SUM MSB. |
| MKW2XDM_CCA1_ED_FNL | CCA1 ED FNL. |
| MKW2XDM_EVENT_TIMER_LSB | Event Timer LSB. |
| MKW2XDM_EVENT_TIMER_MSB | Event Timer MSB. |
| MKW2XDM_EVENT_TIMER_USB | Event Timer USB. |
| MKW2XDM_TIMESTAMP_LSB | Timestamp LSB. |
| MKW2XDM_TIMESTAMP_MSB | Timestamp MSB. |
| MKW2XDM_TIMESTAMP_USB | Timestamp USB. |
| MKW2XDM_T3CMP_LSB | Timer 3 Compare Value LSB. |
| MKW2XDM_T3CMP_MSB | Timer 3 Compare Value MSB. |
| MKW2XDM_T3CMP_USB | Timer 3 Compare Value USB. |
| MKW2XDM_T2PRIMECMP_LSB | Timer 2-Prime Compare Value LSB. |
| MKW2XDM_T2PRIMECMP_MSB | Timer 2-Prime Compare Value MSB. |
| MKW2XDM_T1CMP_LSB | Timer 1 Compare Value LSB. |
| MKW2XDM_T1CMP_MSB | Timer 1 Compare Value MSB. |
| MKW2XDM_T1CMP_USB | Timer 1 Compare Value USB. |
| MKW2XDM_T2CMP_LSB | Timer 2 Compare Value LSB. |
| MKW2XDM_T2CMP_MSB | Timer 2 Compare Value MSB. |
| MKW2XDM_T2CMP_USB | Timer 2 Compare Value USB. |
| MKW2XDM_T4CMP_LSB | Timer 4 Compare Value LSB. |
| MKW2XDM_T4CMP_MSB | Timer 4 Compare Value MSB. |
| MKW2XDM_T4CMP_USB | Timer 4 Compare Value USB. |
| MKW2XDM_PLL_INT0 | PLL Integer Value for PAN0. |
| MKW2XDM_PLL_FRAC0_LSB | PLL Frequency Fractional Value for PAN0. |
| MKW2XDM_PLL_FRAC0_MSB | PLL Frequency Fractional Value for PAN0. |
| MKW2XDM_PA_PWR | PA Power Control (PA_PWR) |
| MKW2XDM_SEQ_STATE | Sequence Manager State. |
| MKW2XDM_LQI_VALUE | Link Quality Indicator. |
| MKW2XDM_RSSI_CCA_CNT | RSSI CCA CNT. |
| MKW2XDM_OVERWRITE_VER | Overwrite Version Number. |
| MKW2XDM_CLK_OUT_CTRL | CLK_OUT Control. |
| MKW2XDM_PWR_MODES | Power Modes. |
| MKW2XDM_IAR_INDEX | IAR Index. |
| MKW2XDM_IAR_DATA | IAR Data. |
Definition at line 89 of file kw2xrf_reg.h.
◆ mkw2xdrf_iregister
| enum mkw2xdrf_iregister |
| Enumerator | |
|---|---|
| MKW2XDMI_PART_ID | Part Identification. |
| MKW2XDMI_XTAL_TRIM | XTAL 32 MHz Trim. |
| MKW2XDMI_MACPANID0_LSB | MAC PAN ID for PAN0. |
| MKW2XDMI_MACPANID0_MSB | MAC PAN ID for PAN0. |
| MKW2XDMI_MACSHORTADDRS0_LSB | MAC Short Address for PAN0. |
| MKW2XDMI_MACSHORTADDRS0_MSB | MAC Short Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_0 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_1 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_2 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_3 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_4 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_5 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_6 | MAC Long Address for PAN0. |
| MKW2XDMI_MACLONGADDRS0_7 | MAC Long Address for PAN0. |
| MKW2XDMI_RX_FRAME_FILTER | Receive Frame Filter. |
| MKW2XDMI_PLL_INT1 | Frequency Integer for PAN1. |
| MKW2XDMI_PLL_FRAC1_LSB | Frequency Fractional Value for PAN1. |
| MKW2XDMI_PLL_FRAC1_MSB | Frequency Fractional Value for PAN1. |
| MKW2XDMI_MACPANID1_LSB | Frequency Fractional Value for PAN1. |
| MKW2XDMI_MACPANID1_MSB | Frequency Fractional Value for PAN1. |
| MKW2XDMI_MACSHORTADDRS1_LSB | MAC Short Address for PAN1. |
| MKW2XDMI_MACSHORTADDRS1_MSB | MAC Short Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_0 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_1 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_2 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_3 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_4 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_5 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_6 | MAC Long Address for PAN1. |
| MKW2XDMI_MACLONGADDRS1_7 | MAC Long Address for PAN1. |
| MKW2XDMI_DUAL_PAN_CTRL | Dual PAN Control. |
| MKW2XDMI_DUAL_PAN_DWELL | Channel Frequency Dwell Time. |
| MKW2XDMI_DUAL_PAN_STS | Dual PAN Status. |
| MKW2XDMI_CCA1_THRESH | Clear Channel Assessment 1 Threshold. |
| MKW2XDMI_CCA1_ED_OFFSET_COMP | Clear Channel Assessment / ED Offset Computation. |
| MKW2XDMI_LQI_OFFSET_COMP | LQI Offset Computation. |
| MKW2XDMI_CCA_CTRL | CCA Control. |
| MKW2XDMI_CCA2_CORR_PEAKS | Clear Channel Assessment 2 Threshold Peak Compare. |
| MKW2XDMI_CCA2_THRESH | Clear Channel Assessment 2 Threshold. |
| MKW2XDMI_TMR_PRESCALE | Event Timer Time Base. |
| MKW2XDMI_GPIO_DATA | GPIO Data. |
| MKW2XDMI_GPIO_DIR | GPIO Direction Control. |
| MKW2XDMI_GPIO_PUL_EN | GPIO Pullup Enable. |
| MKW2XDMI_GPIO_SEL | GPIO Pullup Select. |
| MKW2XDMI_GPIO_DS | GPIO Drive Strength. |
| MKW2XDMI_ANT_PAD_CTRL | Antenna Control. |
| MKW2XDMI_MISC_PAD_CTRL | Miscellaneous Pad Control. |
| MKW2XDMI_ANT_AGC_CTRL | Antenna AGC and FAD Control. |
| MKW2XDMI_LPPS_CTRL | LPPS_CTRL. |
Definition at line 245 of file kw2xrf_reg.h.
