kinetis_common/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define HAVE_GPIO_T
35 typedef uint16_t gpio_t;
41 #define GPIO_UNDEF (0xffff)
42 
46 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
47 
51 #define CPUID_ADDR (&SIM->UIDH)
52 
55 #define CPUID_LEN (16U)
56 
66 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
67 
71 #define PWM_CHAN_MAX (4U)
72 
79 #define SPI_HWCS(x) (x)
80 
84 #define SPI_HWCS_NUMOF (5)
85 
90 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
91 #define PERIPH_SPI_NEEDS_TRANSFER_REG
92 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
93 
98 #define PM_NUM_MODES (1U)
99 
104 #define PM_BLOCKER_INITIAL { .val_u32 = 0x01010101 }
105 
106 #ifndef DOXYGEN
107 
111 #define HAVE_GPIO_MODE_T
112 typedef enum {
113  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
114  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
115  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
116  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
117  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
118  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
119 } gpio_mode_t;
121 #endif /* ndef DOXYGEN */
122 
128 typedef enum {
129  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
130  GPIO_AF_GPIO = PORT_PCR_MUX(1),
131  GPIO_AF_2 = PORT_PCR_MUX(2),
132  GPIO_AF_3 = PORT_PCR_MUX(3),
133  GPIO_AF_4 = PORT_PCR_MUX(4),
134  GPIO_AF_5 = PORT_PCR_MUX(5),
135  GPIO_AF_6 = PORT_PCR_MUX(6),
136  GPIO_AF_7 = PORT_PCR_MUX(7),
137  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
138  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
139  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
140 } gpio_pcr_t;
141 
142 #ifndef DOXYGEN
143 
147 #define HAVE_GPIO_FLANK_T
148 typedef enum {
149  GPIO_RISING = PORT_PCR_IRQC(0x9),
150  GPIO_FALLING = PORT_PCR_IRQC(0xa),
151  GPIO_BOTH = PORT_PCR_IRQC(0xb),
152 } gpio_flank_t;
154 #endif /* ndef DOXYGEN */
155 
161 enum {
162  PORT_A = 0,
163  PORT_B = 1,
164  PORT_C = 2,
165  PORT_D = 3,
166  PORT_E = 4,
167  PORT_F = 5,
168  PORT_G = 6,
170 };
171 
172 #ifndef DOXYGEN
173 
177 #define HAVE_ADC_RES_T
178 typedef enum {
179  ADC_RES_6BIT = (0xfe),
180  ADC_RES_8BIT = ADC_CFG1_MODE(0),
181  ADC_RES_10BIT = ADC_CFG1_MODE(2),
182  ADC_RES_12BIT = ADC_CFG1_MODE(1),
183  ADC_RES_14BIT = (0xff),
184  ADC_RES_16BIT = ADC_CFG1_MODE(3)
185 } adc_res_t;
192 #define HAVE_PWM_MODE_T
193 typedef enum {
194  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
195  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
196  PWM_CENTER = (FTM_CnSC_MSB_MASK)
197 } pwm_mode_t;
199 #endif /* ndef DOXYGEN */
200 
201 #ifndef DOXYGEN
202 
206 #define HAVE_SPI_MODE_T
207 typedef enum {
208  SPI_MODE_0 = 0,
209  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
210  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
211  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
212 } spi_mode_t;
214 #endif /* ndef DOXYGEN */
215 
219 typedef struct {
220  ADC_Type *dev;
221  gpio_t pin;
223  uint8_t chan;
224 } adc_conf_t;
225 
229 typedef struct {
231  DAC_Type *dev;
233  uint32_t volatile *clk_gate;
234 } dac_conf_t;
235 
239 typedef struct {
241  uint8_t prescaler_ch;
243  uint8_t count_ch;
244 } pit_conf_t;
245 
249 typedef struct {
251  LPTMR_Type *dev;
253  uint32_t volatile *clk_gate;
255  uint8_t index;
256 } lptmr_conf_t;
257 
261 typedef struct {
262  FTM_Type* ftm;
263  struct {
264  gpio_t pin;
265  uint8_t af;
266  uint8_t ftm_chan;
267  } chan[PWM_CHAN_MAX];
268  uint8_t chan_numof;
269  uint8_t ftm_num;
270 } pwm_conf_t;
271 
275 typedef struct {
276  SPI_Type *dev;
277  gpio_t pin_miso;
278  gpio_t pin_mosi;
279  gpio_t pin_clk;
280  gpio_t pin_cs[SPI_HWCS_NUMOF];
282  uint32_t simmask;
283 } spi_conf_t;
284 
288 enum {
291 };
292 
297 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
298 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
299 
304 typedef struct {
305  UART_Type *dev;
306  volatile uint32_t *clken;
307  uint32_t freq;
308  gpio_t pin_rx;
309  gpio_t pin_tx;
310  uint32_t pcr_rx;
311  uint32_t pcr_tx;
313 } uart_conf_t;
314 
321 void gpio_init_port(gpio_t pin, uint32_t pcr);
322 
323 #ifdef __cplusplus
324 }
325 #endif
326 
327 #endif /* PERIPH_CPU_H */
328 
volatile uint32_t * clken
Clock enable bitband register address.
uint8_t ftm_num
FTM number used.
emit interrupt on rising flank
Definition: gpio.h:114
uint32_t volatile * clk_gate
Pointer to module clock gate bit in bitband region, use BITBAND_REGADDR()
IRQn_Type irqn
IRQ number for this module.
ADC resolution: 12 bit.
CPU specific timer PIT module configuration.
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:106
use alternate function 7
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
uint8_t af
alternate function mapping
enum IRQn IRQn_Type
Interrupt Number Definition.
uint8_t index
LPTMR device index.
SPI_Type * dev
SPI device to use.
gpio_pcr_t pcr
alternate pin function values
LPTMR_Type * dev
LPTMR device base pointer.
DAC_Type * dev
DAC device base pointer.
overall number of available ports
use alternate function 3
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
uint8_t chan
ADC channel.
PWM configuration structure.
UART_Type * dev
Pointer to module hardware registers.
gpio_pcr_t
Define a condensed set of PORT PCR values.
emit interrupt on both flanks
Definition: gpio.h:115
uint8_t chan_numof
number of actually configured channels
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
#define PWM_CHAN_MAX
Define the maximum number of PWM channels that can be configured.
ADC resolution: 14 bit (not supported)
ADC resolution: 10 bit.
ADC_Type * dev
ADC device.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t pin_clk
CLK pin used.
ADC resolution: 16 bit (not supported)
use alternate function 2
ADC resolution: 8 bit.
ADC resolution: 6 bit.
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
Definition: gpio.h:113
gpio_t pin
GPIO pin used, set to GPIO_UNDEF.
uint8_t ftm_chan
the actual FTM channel used
input, pull-up
uint32_t pcr_tx
Pin configuration register bits for TX.
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
UART device configuration.
input, no pull
CPU specific DAC configuration.
uint32_t volatile * clk_gate
Pointer to module clock gate bit in bitband region, use BITBAND_REGADDR()
uint32_t pcr_rx
Pin configuration register bits for RX.
not supported
use alternate function 4
SPI configuration data structure.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
CPU specific timer LPTMR module configuration.
input, pull-down
CPU specific ADC configuration.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
use alternate function 6
use pin as analog input
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
use alternate function 5