kinetis_common/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include <stdint.h>
23 #include <stdbool.h>
24 
25 #include "cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
35 #define HAVE_GPIO_T
36 typedef uint16_t gpio_t;
42 #define GPIO_UNDEF (0xffff)
43 
47 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
48 
52 #define CPUID_ADDR (&SIM->UIDH)
53 
56 #define CPUID_LEN (16U)
57 
67 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
68 
72 #define PWM_CHAN_MAX (4U)
73 
80 #define SPI_HWCS(x) (x)
81 
85 #define SPI_HWCS_NUMOF (5)
86 
91 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
92 #define PERIPH_SPI_NEEDS_TRANSFER_REG
93 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
94 
99 #define PERIPH_TIMER_PROVIDES_SET
100 
104 #define PM_NUM_MODES (1U)
105 
110 #define PM_BLOCKER_INITIAL { .val_u32 = 0x01010101 }
111 
112 #ifndef DOXYGEN
113 
117 #define HAVE_GPIO_MODE_T
118 typedef enum {
119  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
120  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
121  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
122  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
123  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
124  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
125 } gpio_mode_t;
127 #endif /* ndef DOXYGEN */
128 
134 typedef enum {
135  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
136  GPIO_AF_GPIO = PORT_PCR_MUX(1),
137  GPIO_AF_2 = PORT_PCR_MUX(2),
138  GPIO_AF_3 = PORT_PCR_MUX(3),
139  GPIO_AF_4 = PORT_PCR_MUX(4),
140  GPIO_AF_5 = PORT_PCR_MUX(5),
141  GPIO_AF_6 = PORT_PCR_MUX(6),
142  GPIO_AF_7 = PORT_PCR_MUX(7),
143  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
144  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
145  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
146 } gpio_pcr_t;
147 
148 #ifndef DOXYGEN
149 
153 #define HAVE_GPIO_FLANK_T
154 typedef enum {
155  GPIO_RISING = PORT_PCR_IRQC(0x9),
156  GPIO_FALLING = PORT_PCR_IRQC(0xa),
157  GPIO_BOTH = PORT_PCR_IRQC(0xb),
158 } gpio_flank_t;
160 #endif /* ndef DOXYGEN */
161 
167 enum {
168  PORT_A = 0,
169  PORT_B = 1,
170  PORT_C = 2,
171  PORT_D = 3,
172  PORT_E = 4,
173  PORT_F = 5,
174  PORT_G = 6,
176 };
177 
178 #ifndef DOXYGEN
179 
183 #define HAVE_ADC_RES_T
184 typedef enum {
185  ADC_RES_6BIT = (0xfe),
186  ADC_RES_8BIT = ADC_CFG1_MODE(0),
187  ADC_RES_10BIT = ADC_CFG1_MODE(2),
188  ADC_RES_12BIT = ADC_CFG1_MODE(1),
189  ADC_RES_14BIT = (0xff),
190  ADC_RES_16BIT = ADC_CFG1_MODE(3)
191 } adc_res_t;
198 #define HAVE_PWM_MODE_T
199 typedef enum {
200  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
201  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
202  PWM_CENTER = (FTM_CnSC_MSB_MASK)
203 } pwm_mode_t;
205 #endif /* ndef DOXYGEN */
206 
212 #define UART_MODE_8N1 (0)
213 
214 #define UART_MODE_8E1 (UART_C1_PE_MASK | UART_C1_M_MASK)
215 
216 #define UART_MODE_8O1 (UART_C1_PE_MASK | UART_C1_M_MASK | UART_C1_PT_MASK)
217 
219 #ifndef DOXYGEN
220 
224 #define HAVE_SPI_MODE_T
225 typedef enum {
226  SPI_MODE_0 = 0,
227  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
228  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
229  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
230 } spi_mode_t;
232 #endif /* ndef DOXYGEN */
233 
237 typedef struct {
238  ADC_Type *dev;
239  gpio_t pin;
241  uint8_t chan;
242 } adc_conf_t;
243 
244 #if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
245 
248 typedef struct {
249  DAC_Type *dev;
250  volatile uint32_t *scgc_addr;
251  uint8_t scgc_bit;
252 } dac_conf_t;
253 #endif
254 
258 typedef struct {
260  uint8_t prescaler_ch;
262  uint8_t count_ch;
263 } pit_conf_t;
264 
268 typedef struct {
270  LPTMR_Type *dev;
272  uint8_t irqn;
273 } lptmr_conf_t;
274 
278 typedef struct {
279  FTM_Type* ftm;
280  struct {
281  gpio_t pin;
282  uint8_t af;
283  uint8_t ftm_chan;
284  } chan[PWM_CHAN_MAX];
285  uint8_t chan_numof;
286  uint8_t ftm_num;
287 } pwm_conf_t;
288 
292 typedef struct {
293  SPI_Type *dev;
294  gpio_t pin_miso;
295  gpio_t pin_mosi;
296  gpio_t pin_clk;
297  gpio_t pin_cs[SPI_HWCS_NUMOF];
299  uint32_t simmask;
300 } spi_conf_t;
301 
305 enum {
308 };
309 
314 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
315 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
316 
321 typedef struct {
322  UART_Type *dev;
323  uint32_t freq;
324  gpio_t pin_rx;
325  gpio_t pin_tx;
326  uint32_t pcr_rx;
327  uint32_t pcr_tx;
329  volatile uint32_t *scgc_addr;
330  uint8_t scgc_bit;
331  uint8_t mode;
332 } uart_conf_t;
333 
334 #if !defined(KINETIS_HAVE_PLL)
335 #if defined(MCG_C6_PLLS_MASK) || DOXYGEN
336 
339 #define KINETIS_HAVE_PLL 1
340 #else
341 #define KINETIS_HAVE_PLL 0
342 #endif
343 #endif /* !defined(KINETIS_HAVE_PLL) */
344 
348 typedef enum kinetis_mcg_mode {
355 #if KINETIS_HAVE_PLL
358 #endif
361 
365 typedef enum {
367  KINETIS_MCG_FLL_FACTOR_640 = (MCG_C4_DRST_DRS(0)),
369  KINETIS_MCG_FLL_FACTOR_732 = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
371  KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
373  KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
375  KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
377  KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
379  KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
381  KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
383 
387 typedef enum {
388  KINETIS_MCG_ERC_RANGE_LOW = MCG_C2_RANGE0(0),
389  KINETIS_MCG_ERC_RANGE_HIGH = MCG_C2_RANGE0(1),
390  KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2),
392 
396 typedef struct {
398  uint32_t clkdiv1;
400  kinetis_mcg_mode_t default_mode;
404  uint8_t fcrdiv;
406  uint8_t oscsel;
408  uint8_t clc;
410  uint8_t fll_frdiv;
415 #if KINETIS_HAVE_PLL
416 
417  uint8_t pll_prdiv;
419  uint8_t pll_vdiv;
420 #endif /* KINETIS_HAVE_PLL */
421 
439 
446 void gpio_init_port(gpio_t pin, uint32_t pcr);
447 
448 #ifdef __cplusplus
449 }
450 #endif
451 
452 #endif /* PERIPH_CPU_H */
453 
uint8_t pll_prdiv
PLL ERC divider setting, see reference manual for MCG_C5[PRDIV].
uint8_t clc
Capacitor Load configuration bits, see reference manual for OSC_CR.
uint8_t ftm_num
FTM number used.
emit interrupt on rising flank
IRQn_Type irqn
IRQ number for this module.
ADC resolution: 12 bit.
CPU specific timer PIT module configuration.
PLL Bypassed External Mode.
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:99
enum kinetis_mcg_mode kinetis_mcg_mode_t
Kinetis possible MCG modes.
use alternate function 7
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
uint8_t af
alternate function mapping
enum IRQn IRQn_Type
Interrupt Number Definition.
bool enable_oscillator
External reference clock selection.
SPI_Type * dev
SPI device to use.
kinetis_mcg_erc_range_t erc_range
ERC range setting, see kinetis_mcg_erc_range_t.
gpio_pcr_t pcr
alternate pin function values
uint8_t irqn
IRQn interrupt number.
LPTMR_Type * dev
LPTMR device base pointer.
uint8_t oscsel
Oscillator selection, see reference manual for MCG_C7[OSCSEL].
FLL Bypassed Low Power External Mode.
uint8_t fcrdiv
Fast internal reference clock divider, see reference manual for MCG_SC[FCRDIV].
overall number of available ports
use alternate function 3
FLL Bypassed Internal Mode.
bool select_fast_irc
Use fast internal reference clock for MCGIRCLK.
uint32_t freq
Module clock frequency, usually CLOCK_CORECLOCK or CLOCK_BUSCLOCK.
kinetis_mcg_fll_t
Kinetis MCG FLL multiplier settings.
uint8_t chan
ADC channel.
PWM configuration structure.
uint32_t clkdiv1
Clock divider bitfield setting, see reference manual for SIM_CLKDIV1.
UART_Type * dev
Pointer to module hardware registers.
gpio_pcr_t
Define a condensed set of PORT PCR values.
emit interrupt on both flanks
uint8_t chan_numof
number of actually configured channels
uint8_t pll_vdiv
PLL VCO divider setting, see reference manual for MCG_C6[VDIV0].
bool enable_mcgirclk
Enable MCGIRCLK output from MCG for use as alternate clock in some modules.
#define PWM_CHAN_MAX
Define the maximum number of PWM channels that can be configured.
not supported by hardware
kinetis_mcg_fll_t fll_factor_fei
FLL multiplier when running in FEI mode.
ADC resolution: 10 bit.
ADC_Type * dev
ADC device.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
gpio_t pin_clk
CLK pin used.
not supported by hardware
use alternate function 2
not supported by hardware
not supported by hardware
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
gpio_t pin
GPIO pin used, set to GPIO_UNDEF.
Clock configuration for Kinetis CPUs.
uint8_t ftm_chan
the actual FTM channel used
kinetis_mcg_mode_t default_mode
MCG mode used after initialization, see kinetis_mcg_mode_t.
uint32_t pcr_tx
Pin configuration register bits for TX.
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
UART device configuration.
input, no pull
FLL Bypassed External Mode.
DAC line configuration data.
volatile uint32_t * scgc_addr
Clock enable register, in SIM module.
kinetis_mcg_fll_t fll_factor_fee
FLL multiplier when running in FEE mode.
uint32_t pcr_rx
Pin configuration register bits for RX.
not supported
FLL Bypassed Low Power Internal Mode.
use alternate function 4
SPI module configuration options.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
CPU specific timer LPTMR module configuration.
input, pull-down
uint8_t fll_frdiv
FLL ERC divider setting, see reference manual for MCG_C1[FRDIV].
uint8_t scgc_bit
Clock enable bit, within the register.
kinetis_mcg_mode
Kinetis possible MCG modes.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
kinetis_mcg_erc_range_t
Kinetis FLL external reference clock range settings.
use alternate function 6
use pin as analog input
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
gpio_t pin_rx
RX pin, GPIO_UNDEF disables RX.
use alternate function 5
uint8_t mode
UART mode: data bits, parity, stop bits.