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kinetis_common/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define HAVE_GPIO_T
35 typedef uint16_t gpio_t;
41 #define GPIO_UNDEF (0xffff)
42 
46 #define GPIO_PIN(x, y) (((x + 1) << 12) | (x << 6) | y)
47 
51 #define CPUID_LEN (16U)
52 
62 #define GPIO_MODE(pu, pe, od, out) (pu | (pe << 1) | (od << 5) | (out << 7))
63 
67 #define PWM_CHAN_MAX (4U)
68 
75 #define SPI_HWCS(x) (x)
76 
80 #define SPI_HWCS_NUMOF (5)
81 
86 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
87 #define PERIPH_SPI_NEEDS_TRANSFER_REG
88 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
89 
91 #ifndef DOXYGEN
92 
96 #define HAVE_GPIO_MODE_T
97 typedef enum {
98  GPIO_IN = GPIO_MODE(0, 0, 0, 0),
99  GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),
100  GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),
101  GPIO_OUT = GPIO_MODE(0, 0, 0, 1),
102  GPIO_OD = GPIO_MODE(1, 0, 1, 1),
103  GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),
104 } gpio_mode_t;
106 #endif /* ndef DOXYGEN */
107 
113 typedef enum {
114  GPIO_AF_ANALOG = PORT_PCR_MUX(0),
115  GPIO_AF_GPIO = PORT_PCR_MUX(1),
116  GPIO_AF_2 = PORT_PCR_MUX(2),
117  GPIO_AF_3 = PORT_PCR_MUX(3),
118  GPIO_AF_4 = PORT_PCR_MUX(4),
119  GPIO_AF_5 = PORT_PCR_MUX(5),
120  GPIO_AF_6 = PORT_PCR_MUX(6),
121  GPIO_AF_7 = PORT_PCR_MUX(7),
122  GPIO_PCR_OD = (PORT_PCR_ODE_MASK),
123  GPIO_PCR_PD = (PORT_PCR_PE_MASK),
124  GPIO_PCR_PU = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
125 } gpio_pcr_t;
126 
127 #ifndef DOXYGEN
128 
132 #define HAVE_GPIO_FLANK_T
133 typedef enum {
134  GPIO_RISING = PORT_PCR_IRQC(0x9),
135  GPIO_FALLING = PORT_PCR_IRQC(0xa),
136  GPIO_BOTH = PORT_PCR_IRQC(0xb),
137 } gpio_flank_t;
139 #endif /* ndef DOXYGEN */
140 
146 enum {
147  PORT_A = 0,
148  PORT_B = 1,
149  PORT_C = 2,
150  PORT_D = 3,
151  PORT_E = 4,
152  PORT_F = 5,
153  PORT_G = 6,
155 };
156 
157 #ifndef DOXYGEN
158 
162 #define HAVE_ADC_RES_T
163 typedef enum {
164  ADC_RES_6BIT = (0xfe),
165  ADC_RES_8BIT = ADC_CFG1_MODE(0),
166  ADC_RES_10BIT = ADC_CFG1_MODE(2),
167  ADC_RES_12BIT = ADC_CFG1_MODE(1),
168  ADC_RES_14BIT = (0xff),
169  ADC_RES_16BIT = ADC_CFG1_MODE(3)
170 } adc_res_t;
177 #define HAVE_PWM_MODE_T
178 typedef enum {
179  PWM_LEFT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),
180  PWM_RIGHT = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),
181  PWM_CENTER = (FTM_CnSC_MSB_MASK)
182 } pwm_mode_t;
184 #endif /* ndef DOXYGEN */
185 
186 #ifndef DOXYGEN
187 
191 #define HAVE_SPI_MODE_T
192 typedef enum {
193  SPI_MODE_0 = 0,
194  SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),
195  SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),
196  SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)
197 } spi_mode_t;
199 #endif /* ndef DOXYGEN */
200 
204 typedef struct {
205  ADC_Type *dev;
206  gpio_t pin;
208  uint8_t chan;
209 } adc_conf_t;
210 
214 typedef struct {
216  DAC_Type *dev;
218  uint32_t volatile *clk_gate;
219 } dac_conf_t;
220 
224 typedef struct {
226  uint8_t prescaler_ch;
228  uint8_t count_ch;
229 } pit_conf_t;
230 
234 typedef struct {
236  LPTMR_Type *dev;
238  uint32_t volatile *clk_gate;
240  uint8_t index;
241 } lptmr_conf_t;
242 
246 typedef struct {
247  FTM_Type* ftm;
248  struct {
249  gpio_t pin;
250  uint8_t af;
251  uint8_t ftm_chan;
252  } chan[PWM_CHAN_MAX];
253  uint8_t chan_numof;
254  uint8_t ftm_num;
255 } pwm_conf_t;
256 
260 typedef struct {
261  SPI_Type *dev;
262  gpio_t pin_miso;
263  gpio_t pin_mosi;
264  gpio_t pin_clk;
265  gpio_t pin_cs[SPI_HWCS_NUMOF];
267  uint32_t simmask;
268 } spi_conf_t;
269 
273 enum {
276 };
277 
282 #define TIMER_PIT_DEV(x) (TIMER_DEV(0 + (x)))
283 #define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
284 
292 void gpio_init_port(gpio_t pin, uint32_t pcr);
293 
297 #define PM_NUM_MODES (1U)
298 
299 #ifdef __cplusplus
300 }
301 #endif
302 
303 #endif /* PERIPH_CPU_H */
304 
uint8_t ftm_num
FTM number used.
emit interrupt on rising flank
Definition: gpio.h:114
uint32_t volatile * clk_gate
Pointer to module clock gate bit in bitband region, use BITBAND_REGADDR()
ADC resolution: 12 bit.
CPU specific timer PIT module configuration.
pwm_mode_t
Default PWM mode definition.
Definition: pwm.h:106
use alternate function 7
uint8_t prescaler_ch
Prescaler channel.
gpio_t pin_miso
MISO pin used.
uint8_t af
alternate function mapping
uint8_t index
LPTMR device index.
SPI_Type * dev
SPI device to use.
gpio_pcr_t pcr
alternate pin function values
LPTMR_Type * dev
LPTMR device base pointer.
DAC_Type * dev
DAC device base pointer.
overall number of available ports
use alternate function 3
uint8_t chan
ADC channel.
PWM configuration structure.
gpio_pcr_t
Define a condensed set of PORT PCR values.
emit interrupt on both flanks
Definition: gpio.h:115
uint8_t chan_numof
number of actually configured channels
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:112
#define PWM_CHAN_MAX
Define the maximum number of PWM channels that can be configured.
ADC resolution: 14 bit (not supported)
ADC resolution: 10 bit.
ADC_Type * dev
ADC device.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t pin_clk
CLK pin used.
ADC resolution: 16 bit (not supported)
use alternate function 2
ADC resolution: 8 bit.
ADC resolution: 6 bit.
uint32_t simmask
bit in the SIM register
gpio_t pin_mosi
MOSI pin used.
emit interrupt on falling flank
Definition: gpio.h:113
gpio_t pin
GPIO pin used, set to GPIO_UNDEF.
uint8_t ftm_chan
the actual FTM channel used
input, pull-up
#define SPI_HWCS_NUMOF
Kinetis CPUs have a maximum number of 5 hardware chip select lines.
input, no pull
CPU specific DAC configuration.
uint32_t volatile * clk_gate
Pointer to module clock gate bit in bitband region, use BITBAND_REGADDR()
not supported
use alternate function 4
SPI configuration data structure.
uint8_t count_ch
Counting channel, will be linked to the prescaler channel.
#define GPIO_MODE(pu, pe, od, out)
Generate GPIO mode bitfields.
CPU specific timer LPTMR module configuration.
input, pull-down
CPU specific ADC configuration.
void gpio_init_port(gpio_t pin, uint32_t pcr)
CPU internal function for initializing PORTs.
use alternate function 6
use pin as analog input
gpio_t pin
pin to use, set to GPIO_UNDEF for internal channels
use alternate function 5