Common implementations and headers for mips32r2 compliant devices. More...
|Common implementations and headers for mips32r2 compliant devices. |
|Common CPU definitions for mip32r2 compatable devices. |
|API for supporting External Interrupt Controllers (EIC mode) |
|static void||cpu_print_last_instruction (void)|
|Print the last instruction's address. More...|
|void||eic_irq_configure (int irq_num)|
|Configure and route the interrupt. |
|void||eic_irq_enable (int irq_num)|
|Enable an interrupt. |
|void||eic_irq_disable (int irq_num)|
|Disable an interrupt. |
|void||eic_irq_ack (int irq_num)|
|Acknowledge an interrupt. |
|Configuration of default stack sizes. More...|
|#define||THREAD_STACKSIZE_IDLE (512 + THREAD_EXTRA_STACKSIZE_PRINTF)|
|@ brief Internal Interrupt numbers More...|
|#define EIC_IRQ_TIMER (-1)|
MIPS cores have a few internally generated interrupts from the Timer, Performance Counters and Fast Debug Channel hardware, in EIC mode these become outputs from the core and are connected to the external controller, the external control then loops these back at whichever IPL it decides
We use negative numbers to represent these, leaving positive numbers free for the SoC specific interrupts
|#define THREAD_EXTRA_STACKSIZE_PRINTF (1024)|
printf takes a pretty tortured route through the C lib then via UHI syscall exception to end up at the UART driver.
When debugging timer code we get printfs on the idle threads stack which can easily blow its limits.
Note code must be compiled at -Os with these values, using -O0 you'll overflow these stacks.
NO ISR stack is in use yet, interrupt use the current running stack hence the big-ish default stack size.