Kinetis SPI driver for MCUs with Cortex-M4 core. More...

If necessary, it is possible to define two RIOT SPI buses for each Kinetis hardware SPI module by specifying different CTAS (timing register number) for the two buses. It is then possible to initialize the two RIOT SPI buses with different baud rates or polarity settings.

SPI_x_INDEX should be set to the index on the hardware module used (SPI0 => 0, SPI1 => 1 etc). spi_acquire and spi_release will share the same lock for all SPI buses defined with the same SPI_x_INDEX.

Finer tuning of timings than the RIOT SPI API is capable of is supported by setting macros SPI_0_TCSC_FREQ, SPI_0_TASC_FREQ, SPI_0_TDT_FREQ. These macros define the desired maximum frequency of the tCSC, tASC, and tDT SPI timings (i.e. reciprocal of time). See the reference manual for your Kinetis CPU (Chapter: "SPI module, Functional description, Module baud rate and clock delay generation") for a description of each delay. Set to 0 or leave unset to default to using the same delay timing as the baudrate.

SPI Configuration Example (for periph_conf.h):

// SPI 0 device config
#define SPI_0_DEV               SPI0
#define SPI_0_INDEX             0
#define SPI_0_CTAS              0
#define SPI_0_CLKEN()           (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS()          (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ               SPI0_IRQn
#define SPI_0_IRQ_HANDLER       isr_spi0
#define SPI_0_FREQ              (48e6)

// SPI 0 pin configuration
#define SPI_0_SCK_PORT          PORTC
#define SPI_0_SOUT_PORT         PORTC
#define SPI_0_SIN_PORT          PORTC
#define SPI_0_PCS0_PORT         PORTC

#define SPI_0_SCK_PORT_CLKEN()  (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_SOUT_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_SIN_PORT_CLKEN()  (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_PCS0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))

#define SPI_0_SCK_AF            2
#define SPI_0_SOUT_AF           2
#define SPI_0_SIN_AF            2
#define SPI_0_PCS0_AF           2

#define SPI_0_PCS0_PIN          4
#define SPI_0_SCK_PIN           5
#define SPI_0_SOUT_PIN          6
#define SPI_0_SIN_PIN           7

#define SPI_0_PCS0_ACTIVE_LOW   1

Alternative Configuration Example:

// SPI 0 device config
#define SPI_0_DEV               SPI0
#define SPI_0_INDEX             0
#define SPI_0_CTAS              0
#define SPI_0_CLKEN()           (SIM->SCGC6 |= (SIM_SCGC6_SPI0_MASK))
#define SPI_0_CLKDIS()          (SIM->SCGC6 &= ~(SIM_SCGC6_SPI0_MASK))
#define SPI_0_IRQ               SPI0_IRQn
#define SPI_0_IRQ_HANDLER       isr_spi0
#define SPI_0_FREQ              (48e6)

// SPI 0 pin configuration
#define SPI_0_PORT              PORTC
#define SPI_0_PORT_CLKEN()      (SIM->SCGC5 |= (SIM_SCGC5_PORTC_MASK))
#define SPI_0_AF                2

#define SPI_0_PCS0_PIN          4
#define SPI_0_SCK_PIN           5
#define SPI_0_SOUT_PIN          6
#define SPI_0_SIN_PIN           7

#define SPI_0_PCS0_ACTIVE_LOW   1

It is possible to use the hardware CS, currently only for the PCS0:

#define KINETIS_SPI_USE_HW_CS   1