Freescale K64F MCU

CPU specific implementations for the Freescale K64F Kinetis Cortex-M4 MCU. More...

Detailed Description

Files

file  cpu/k64f/include/cpu_conf.h
 Implementation specific CPU configuration options.
 

Macros

#define LPTIMER_CLKSRC   LPTIMER_CLKSRC_LPO
 MCU specific Low Power Timer settings.
 
#define LPTIMER_DEV   (LPTMR0)
 LPTIMER hardware module.
 
#define LPTIMER_CLKEN()   (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK)
 Enable LPTMR0 clock gate.
 
#define LPTIMER_CLKDIS()   (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK)
 Disable LPTMR0 clock gate.
 
#define CPU_DEFAULT_IRQ_PRIO   (1U)
 ARM Cortex-M specific CPU configuration.
 
#define CPU_IRQ_NUMOF   (86U)
 
#define CPU_FLASH_BASE   (0x00000000)
 

GPIO pin mux function numbers

#define PIN_MUX_FUNCTION_ANALOG   0
 
#define PIN_MUX_FUNCTION_GPIO   1
 

GPIO interrupt flank settings

#define PIN_INTERRUPT_RISING   0b1001
 
#define PIN_INTERRUPT_FALLING   0b1010
 
#define PIN_INTERRUPT_EDGE   0b1011
 

PORT module clock gates

#define PORTA_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
 
#define PORTB_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
 
#define PORTC_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
 
#define PORTD_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
 
#define PORTE_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))