Support for the STM32 Nucleo-F446.
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Support for the STM32 Nucleo-F446.
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- Note
- This is auto-generated from
cpu/stm32_common/dist/clk_conf/clk_conf.c
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#define | CLOCK_CORECLOCK (180000000U) |
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#define | CLOCK_HSE (8000000U) |
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#define | CLOCK_LSE (1) |
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#define | CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 |
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#define | CLOCK_AHB (CLOCK_CORECLOCK / 1) |
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#define | CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */ |
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#define | CLOCK_APB1 (CLOCK_CORECLOCK / 4) |
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#define | CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */ |
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#define | CLOCK_APB2 (CLOCK_CORECLOCK / 2) |
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#define | CLOCK_PLL_M (4) |
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#define | CLOCK_PLL_N (180) |
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#define | CLOCK_PLL_P (2) |
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#define | CLOCK_PLL_Q (0) |
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#define | CLOCK_ENABLE_PLL_SAI (1) |
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#define | CLOCK_PLL_SAI_M (4) |
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#define | CLOCK_PLL_SAI_N (192) |
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#define | CLOCK_PLL_SAI_P (8) |
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#define | CLOCK_PLL_SAI_Q (0) |
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#define | CLOCK_USE_ALT_48MHZ (1) |
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static const timer_conf_t | timer_config [] |
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#define | TIMER_0_ISR isr_tim5 |
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#define | TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) |
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static const uart_conf_t | uart_config [] |
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#define | UART_0_ISR (isr_usart2) |
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#define | UART_0_DMA_ISR (isr_dma1_stream6) |
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#define | UART_1_ISR (isr_usart3) |
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#define | UART_1_DMA_ISR (isr_dma1_stream5) |
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#define | UART_2_ISR (isr_usart1) |
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#define | UART_2_DMA_ISR (isr_dma1_stream4) |
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#define | UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) |
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static const pwm_conf_t | pwm_config [] |
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#define | PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) |
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static const qdec_conf_t | qdec_config [] |
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#define | QDEC_0_ISR isr_tim3 |
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#define | QDEC_1_ISR isr_tim4 |
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#define | QDEC_NUMOF (sizeof(qdec_config) / sizeof(qdec_config[0])) |
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- Note
- The spi_divtable is auto-generated from
cpu/stm32_common/dist/spi_divtable/spi_divtable.c
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static const uint8_t | spi_divtable [2][5] |
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static const spi_conf_t | spi_config [] |
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#define | SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) |
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#define | I2C_NUMOF (1U) |
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#define | I2C_0_EN 1 |
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#define | I2C_IRQ_PRIO 1 |
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#define | I2C_APBCLK (CLOCK_APB1) |
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#define | I2C_0_DEV I2C1 |
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#define | I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN)) |
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#define | I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN)) |
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#define | I2C_0_EVT_IRQ I2C1_EV_IRQn |
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#define | I2C_0_EVT_ISR isr_i2c1_ev |
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#define | I2C_0_ERR_IRQ I2C1_ER_IRQn |
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#define | I2C_0_ERR_ISR isr_i2c1_er |
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#define | I2C_0_SCL_PORT GPIOB |
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#define | I2C_0_SCL_PIN 8 |
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#define | I2C_0_SCL_AF 4 |
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#define | I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN)) |
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#define | I2C_0_SDA_PORT GPIOB |
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#define | I2C_0_SDA_PIN 9 |
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#define | I2C_0_SDA_AF 4 |
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#define | I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN)) |
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Note that we do not configure all ADC channels, and not in the STM32F446 order.
Instead, we just define 6 ADC channels, for the Nucleo Arduino header pins A0-A5
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#define | ADC_NUMOF (6U) |
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#define | ADC_CONFIG |
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◆ ADC_CONFIG
◆ pwm_config
Initial value:= {
{
.dev = TIM2,
.rcc_mask = RCC_APB1ENR_TIM2EN,
},
{
.dev = TIM8,
.rcc_mask = RCC_APB2ENR_TIM8EN,
},
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition at line 153 of file boards/nucleo-f446/include/periph_conf.h.
◆ qdec_config
Initial value:= {
{
.dev = TIM3,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM3EN,
.irqn = TIM3_IRQn
},
{
.dev = TIM4,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM4EN,
.irqn = TIM4_IRQn
},
}
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition at line 183 of file boards/nucleo-f446/include/periph_conf.h.
◆ spi_divtable
const uint8_t spi_divtable[2][5] |
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static |
◆ timer_config