periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include "cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 #define TIMER_UNDEF (0xffffffff)
32 
37 #define HAVE_TIMER_T
38 typedef uint32_t tim_t;
44 #define CPUID_ADDR (&DEVINFO->UNIQUEL)
45 
48 #define CPUID_LEN (8U)
49 
56 typedef struct {
57  TIMER_TypeDef *prescaler;
58  TIMER_TypeDef *timer;
59  uint8_t pre_cmu;
61  uint8_t irqn;
62 } timer_conf_t;
63 
68 #define HAVE_GPIO_T
69 typedef uint32_t gpio_t;
75 #define GPIO_UNDEF (0xffffffff)
76 
81 #define GPIO_PIN(x, y) ((x << 4) | y)
82 
86 enum {
87  PA = 0,
88  PB = 1,
89  PC = 2,
90  PD = 3,
91  PE = 4,
92  PF = 5
93 };
94 
95 #ifndef DOXYGEN
96 
100 #define HAVE_GPIO_MODE_T
101 typedef enum {
102  GPIO_IN = _GPIO_P_MODEL_MODE0_INPUT,
103  GPIO_IN_PD = _GPIO_P_MODEL_MODE0_INPUTPULL,
104  GPIO_IN_PU = _GPIO_P_MODEL_MODE0_INPUTPULL,
105  GPIO_OUT = _GPIO_P_MODEL_MODE0_PUSHPULL,
106  GPIO_OD = _GPIO_P_MODEL_MODE0_WIREDAND,
107  GPIO_OD_PU = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP
108 } gpio_mode_t;
115 #define HAVE_GPIO_FLANK_T
116 typedef enum {
117  GPIO_FALLING = 2,
118  GPIO_RISING = 1,
119  GPIO_BOTH = 3
120 } gpio_flank_t;
122 #endif /* ndef DOXYGEN */
123 
127 typedef struct {
128  USART_TypeDef *dev;
129  gpio_t rx_pin;
130  gpio_t tx_pin;
131  uint8_t loc;
132  uint8_t cmu;
133  uint8_t irq;
134 } uart_conf_t;
135 
136 #ifdef __cplusplus
137 }
138 #endif
139 
140 #endif /* PERIPH_CPU_H */
141 
configure as output in push-pull mode
Definition: gpio.h:117
emit interrupt on rising flank
Definition: gpio.h:131
port A
Definition: periph_cpu.h:87
port B
Definition: periph_cpu.h:88
port C
Definition: periph_cpu.h:89
uint8_t irq
the devices base IRQ channel
Definition: periph_cpu.h:133
unsigned int tim_t
Default timer type.
Definition: timer.h:69
TIMER_TypeDef * timer
the higher numbered timer
Definition: periph_cpu.h:58
uint8_t pre_cmu
prescale timer bit in CMU register, the timer bit is deducted from this
Definition: periph_cpu.h:59
uint8_t irqn
number of the higher timer IRQ channel
Definition: periph_cpu.h:61
uint8_t loc
location of USART pins (AF)
Definition: periph_cpu.h:131
emit interrupt on both flanks
Definition: gpio.h:132
gpio_flank_t
Definition of possible active flanks for external interrupt mode.
Definition: gpio.h:129
port D
Definition: periph_cpu.h:90
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
emit interrupt on falling flank
Definition: gpio.h:130
configure as input with pull-up resistor
Definition: gpio.h:116
UART device configuration.
Definition: periph_cpu.h:166
gpio_mode_t
Available pin modes.
Definition: gpio.h:113
configure as input without pull resistor
Definition: gpio.h:114
configure as output in open-drain mode without pull resistor
Definition: gpio.h:118
configure as input with pull-down resistor
Definition: gpio.h:115
uint8_t cmu
the device CMU channel
Definition: periph_cpu.h:132
port F
Definition: periph_cpu.h:92
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:120
Timer configuration.
Definition: periph_cpu.h:286
TIMER_TypeDef * prescaler
the lower numbered neighboring timer
Definition: periph_cpu.h:57
port E
Definition: periph_cpu.h:91
USART_TypeDef * dev
USART device used.
Definition: periph_cpu.h:128