encx24j600_defines.h
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1 /*
2  * Copyright (C) 2015 Ell-i open source co-operative
3  * Kaspar Schleiser <kaspar@schleiser.de>
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
20 #ifndef ENCX24J600_REGS_H
21 #define ENCX24J600_REGS_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 #define ENC_RCR 0x00 /* read control register */
32 #define ENC_WCR 0x04 /* write control register */
33 
34 #define ENC_RCRU 0x20 /* read control register unbanked */
35 #define ENC_WCRU 0x22 /* write control register unbanked */
36 
37 #define ENC_BFSU 0x24 /* set bits unbanked */
38 #define ENC_BFCU 0x26 /* clear bits unbanked */
39 
40 #define ENC_RGPDATA 0x28 /* Read EGPDATA */
41 #define ENC_WGPDATA 0x2a /* Write EGPDATA */
42 
43 #define ENC_RRXDATA 0x2c /* Read ERXDATA */
44 #define ENC_WRXDATA 0x2e /* Write ERXDATA */
45 
46 #define ENC_RUDADATA 0x30 /* Read EUDADATA */
47 #define ENC_WUDADATA 0x32 /* Write EUDADATA */
48 
49 #define ENC_BFS 0x80 /* Bit Field Set */
50 #define ENC_BFC 0xa0 /* Bit Field Clear */
51 
52 #define ENC_SETETHRST 0xca /* System Reset */
53 #define ENC_SETPKTDEC 0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
54 #define ENC_ENABLERX 0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
55 #define ENC_DISABLERX 0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
56 #define ENC_SETEIE 0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
57 #define ENC_CLREIE 0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
58 
59 #define ENC_B0SEL 0xc0 /* select bank 0 */
60 #define ENC_B1SEL 0xc2 /* select bank 0 */
61 #define ENC_B2SEL 0xc4 /* select bank 0 */
62 #define ENC_B3SEL 0xc6 /* select bank 0 */
63 #define ENC_RBSEL 0xc8 /* Read Bank Select */
64 
65 #define ENC_SETTXRTS 0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
66 
72 #define ENC_ETXST 0x00
73 #define ENC_ETXLEN 0x02
74 #define ENC_ERXST 0x04
75 #define ENC_ERXTAIL 0x06
76 #define ENC_ERXHEAD 0x08
77 #define ENC_ETXSTAT 0x12
78 #define ENC_ETXWIRE 0x14
79 #define ENC_EUDAST 0x16
80 #define ENC_ESTAT 0x1a
81 #define ENC_EIR 0x1c /* Interrupt Flag Register */
82 #define ENC_ECON1 0x1e
83 
84 #define ENC_ERXFCON 0x34 /* Receive filter control register */
85 
86 #define ENC_MACON2 0x42
87 #define ENC_MAMXFL 0x4a /* MAC maximum frame length */
88 
89 #define ENC_MAADR3 0x60 /* MAC address byte 5&6 */
90 #define ENC_MAADR2 0x62 /* MAC address byte 3&4 */
91 #define ENC_MAADR1 0x64 /* MAC address byte 1&2 */
92 
93 #define ENC_MIWR 0x66
94 #define ENC_MIREGADR 0x54
95 
96 #define ENC_ECON2 0x6e
97 
98 #define ENC_EIE 0x72 /* Interrupt Enable Register */
99 
100 #define ENC_EGPRDPT 0x86 /* General Purpose SRAM read pointer */
101 #define ENC_EGPWRPT 0x88 /* General Purpose SRAM write pointer */
102 
103 #define ENC_ERXRDPT 0x8a /* RX buffer read pointer */
104 #define ENC_ERXWRPT 0x8c /* RX buffer write pointer */
105 
114 #define ENC_PHCON1 0x00
115 #define ENC_PHSTAT1 0x01
116 #define ENC_PHANA 0x04
117 #define ENC_PHANLPA 0x05
118 #define ENC_PHANE 0x06
119 #define ENC_PHCON2 0x11
120 #define ENC_PHSTAT2 0x1b
121 #define ENC_PHSTAT3 0x1f
122 
128 #define ENC_PHYLNK (1<<8)
129 #define ENC_CLKRDY (1<<12)
130 
136 #define ENC_RXEN (1<<0)
137 #define ENC_TXRTS (1<<1)
138 #define ENC_DMANOCS (1<<2)
139 #define ENC_DMACSSD (1<<3)
140 #define ENC_DMACPY (1<<4)
141 #define ENC_DMAST (1<<5)
142 #define ENC_FCOP0 (1<<6)
143 #define ENC_FCOP1 (1<<7)
144 #define ENC_PKTDEC (1<<8)
145 #define ENC_AESOP0 (1<<9)
146 #define ENC_AESOP1 (1<<10)
147 #define ENC_AESST (1<<11)
148 #define ENC_HASHLST (1<<12)
149 #define ENC_HASHOP (1<<13)
150 #define ENC_HASHEN (1<<14)
151 #define ENC_MODEXST (1<<15)
152 
158 #define ENC_ETHRST (1<<4)
159 #define ENC_AUTOFC (1<<7) /* automatic flow control enable bit */
160 
166 #define ENC_PCFULIE (1<<0)
167 #define ENC_RXABTIE (1<<1)
168 #define ENC_TXABTIE (1<<2)
169 #define ENC_TXIE (1<<3)
170 #define ENC_DMAIE (1<<5)
171 #define ENC_PKTIE (1<<6)
172 #define ENC_LINKIE (1<<11)
173 #define ENC_AESIE (1<<12)
174 #define ENC_HASHIE (1<<13)
175 #define ENC_MODEXIE (1<<14)
176 #define ENC_INTIE (1<<15)
177 
183 #define ENC_PCFULIF (1<<0)
184 #define ENC_RXABTIF (1<<1)
185 #define ENC_TXABTIF (1<<2)
186 #define ENC_TXIF (1<<3)
187 #define ENC_DMAIF (1<<5)
188 #define ENC_PKTIF (1<<6)
189 #define ENC_LINKIF (1<<11)
190 #define ENC_AESIF (1<<12)
191 #define ENC_HASHIF (1<<13)
192 #define ENC_MODEXIF (1<<14)
193 #define ENC_CRYPTEN (1<<15)
194 
199 #define ENC_MCEN (1<<1)
200 
202 #ifdef __cplusplus
203 }
204 #endif
205 #endif /* ENCX24J600_REGS_H */
206