cpu/kw2xd/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
29 #ifndef CPU_CONF_H
30 #define CPU_CONF_H
31 
32 #ifdef CPU_MODEL_KW21D256
33 #include "vendor/MKW22D5.h"
34 #elif CPU_MODEL_KW21D512
35 #include "vendor/MKW22D5.h"
36 #elif CPU_MODEL_KW22D512
37 #include "vendor/MKW22D5.h"
38 #else
39 #error "undefined CPU_MODEL"
40 #endif
41 
42 #include "cpu_conf_kinetis.h"
43 
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif
48 
52 #define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
53 
56 #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
57 #define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
58 #define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
59 #define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
60 #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
61 
68 #define KW2XDRF_PORT_DEV PORTB
69 #define KW2XDRF_PORT PORT_B
70 #define KW2XDRF_GPIO GPIOB
71 #define KW2XDRF_PORT_IRQn PORTB_IRQn
72 
73 #define KW2XDRF_PORT_CLKEN() (PORTB_CLOCK_GATE = 1)
74 #define KW2XDRF_PIN_AF 2
75 #define KW2XDRF_PCS0_PIN 10
76 #define KW2XDRF_SCK_PIN 11
77 #define KW2XDRF_SOUT_PIN 16
78 #define KW2XDRF_SIN_PIN 17
79 #define KW2XDRF_RST_PIN 19
80 #define KW2XDRF_IRQ_PIN 3
81 #define KW2XDRF_CLK_CTRL_PORT PORT_C
82 #define KW2XDRF_CLK_CTRL_PORT_DEV PORTC
83 #define KW2XDRF_CLK_CTRL_GPIO GPIOC
84 #define KW2XDRF_CLK_CTRL_CLKEN() (PORTC_CLOCK_GATE = 1)
85 #define KW2XDRF_CLK_CTRL_PIN 0
89 #ifdef __cplusplus
90 }
91 #endif
92 
93 #endif /* CPU_CONF_H */
94 
CPU specific definitions common to all Kinetis CPUs.